DS92LV16TVHG/NOPB National Semiconductor, DS92LV16TVHG/NOPB Datasheet - Page 3

IC SERDES LVDS 16BIT BUS 80-LQFP

DS92LV16TVHG/NOPB

Manufacturer Part Number
DS92LV16TVHG/NOPB
Description
IC SERDES LVDS 16BIT BUS 80-LQFP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS92LV16TVHG/NOPB

Function
Serializer/Deserializer
Data Rate
2.56Gbps
Input Type
LVTTL/LVCMOS
Output Type
LVTTL, LVCMOS
Number Of Inputs
1
Number Of Outputs
16
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
80-LQFP
No. Of Inputs
16
No. Of Outputs
16
Supply Voltage Range
3.15V To 3.45V
Driver Case Style
QFP
No. Of Pins
80
Msl
MSL 3 - 168 Hours
Filter Terminals
SMD
Rohs Compliant
Yes
Data Rate Max
1280Mbps
For Use With
BLVDS16EVK - BOARD EVAL FOR DS92LV16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
*DS92LV16TVHG
*DS92LV16TVHG/NOPB
DS92LV16TVHG

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS92LV16TVHG/NOPB
Manufacturer:
NSC
Quantity:
251
Part Number:
DS92LV16TVHG/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins)
Symbol
Symbol
Symbol
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
t
t
t
t
V
I
I
t
V
t
CLKT
LLHT
LHLT
t
t
I
I
TCIH
I
CCT
CCX
TCIL
t
V
V
TCP
DIS
DIH
OS
OX
OZ
JIT
OD
OS
OD
OS
DIN (0-15) Setup to TCLK
Transmit Clock High Time
Transmit Clock Low Time
Total Supply Current (includes
Bus LVDS Low-to-High
Bus LVDS High-to-Low
Transmit Clock Period
TCLK Input Transition
Output Short Circuit Current
Supply Current Powerdown
DIN (0-15) Hold from
Output Differential Voltage
Output Differential Voltage
Offset Voltage Unbalance
Power-Off Output Current
Tri-State Output Current
TCLK Input Jitter
Transition Time
Transition Time
Parameter
Parameter
Offset Voltage
(DO+) - (DO-)
load current)
TCLK
Time
Parameter
Unbalance
C
C
L
L
=10pF to GND
=10pF to GND
Conditions
Conditions
R
(Continued)
R
TXPWDN and DEN =
C
C
RL = 100 , Figure 17
VDD = 0V, DO = 0V
TXPWDN or DEN =
Figure 3
Figure 6
L
0.8V, DO = 0V OR
DO = 0V, Din = H,
L
L
L
PWRDN = 0.8V,
= 100 ,
= 100
= 15 pF, R
= 15 pF, R
REN = 0.8V
Conditions
or 3.6V
VDD
2.4V
L
L
= 100 f = 80 MHz, PRBS15
= 100
3
f = 80 MHz, Worse
0.4T
0.4T
12.5
Min
Min
2.4
(Checker-board
0
case pattern
DO+, DO-
Pin/Freq.
pattern)
pattern
0.5T
0.5T
Typ
Typ
0.2
0.2
T
3
1.05
Min
350
-35
-10
-10
Max
0.6T
0.6T
Max
0.35
Typ
500
209
225
±
±
0.4
0.4
1.2
2.7
-50
40
80
6
2
1
1
www.national.com
Max
1.25
550
320
-70
1.0
15
15
10
10
(RMS)
Units
Units
Units
ns
ns
ns
ns
ps
ns
ns
ns
ns
mV
mV
mV
mA
mA
mA
mA
µA
µA
V

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