DS92LV16TVHG/NOPB National Semiconductor, DS92LV16TVHG/NOPB Datasheet - Page 5

• Manufacturer Part Number: DS92LV16TVHG/NOPB
• Description: IC SERDES LVDS 16BIT BUS 80-LQFP
• Manufacturer: National Semiconductor

Specifications of DS92LV16TVHG/NOPB

• Function: Serializer/Deserializer
• Data Rate: 2.56Gbps
• Input Type: LVTTL/LVCMOS
• Output Type: LVTTL, LVCMOS
• Number Of Inputs: 1
• Number Of Outputs: 16
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• No. Of Inputs: 16
• No. Of Outputs: 16
• Supply Voltage Range: 3.15V To 3.45V
• Driver Case Style: QFP
• No. Of Pins: 80
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Data Rate Max: 1280Mbps
• For Use With: BLVDS16EVK - BOARD EVAL FOR DS92LV16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS92LV16TVHG; *DS92LV16TVHG/NOPB; DS92LV16TVHG

Symbol
t
t
RNMI-R
t
t
RNMI-L
DSR1
DSR2
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: For the purpose of specifying deserializer PLL performance tDSR1 and tDSR2 are specified with the REFCLK running and stable, and specific conditions
of the incoming data stream (SYNCPATs). It is recommended that the derserializer be initialized using either tDSR1 timing or tDSR2 timing. tDSR1 is the time
required for the deserializer to indicate lock upon power-up or when leaving the power-down mode. Synchronization patterns should be sent to the device before
initiating either condition. tDSR2 is the time required to indicate lock for the powered-up and enabled deserializer when the input (RI+ and RI-) conditions change
from not receiving data to receiving synchronization patterns (SYNCPATs).
Note 6: tRNMI is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement
in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: Sync pattern is a fixed pattern with 8-bit of data high followed by 8-bit of data low.
Noise Margin Right
Noise Margin Left
Ideal Deserializer
Ideal Deserializer
Deserializer PLL
Deserializer PLL
PWRDWN (with
Lock Time from
Lock time from
SYNCPAT)
Parameter
SYNCPAT
CC
= 3.3V and T
Conditions
Figure 16
Figure 16
(Note 7)
(Note 6)
(Note 6)
A
= +25˚C.
Pin/Freq.
80 MHz
80 MHz
35 MHz
80 MHz
35 MHz
80 MHz
35MHz
35MHz
5
(Continued)
−630
−230
Min
Typ
3.7
1.9
1.5
0.9
+630
+230
Max
10
4
5
2
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Units
µs
µs
µs
µs
ps
ps
ps
ps