MAX9206EAI+ Maxim Integrated Products, MAX9206EAI+ Datasheet - Page 11

IC DESERIALIZER LVDS 28-SSOP

MAX9206EAI+

Manufacturer Part Number
MAX9206EAI+
Description
IC DESERIALIZER LVDS 28-SSOP
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX9206EAI+

Function
Deserializer
Data Rate
660Mbps
Input Type
LVDS
Output Type
LVTTL, LVCMOS
Number Of Inputs
1
Number Of Outputs
10
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SSOP
Input Current
+/- 15 uA
Input Voltage Range (max)
3.6 V
Interface Type
Parallel LVCMOS/LVTTL
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Settling Time
3000 ps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 2. Input/Output Function Table
X = Don’t care.
The MAX9206/MAX9208 deserializers can operate in a
variety of topologies. Examples of double-terminated
point-to-point and point-to-point broadcast are shown
in Figures 10 and 11. Use 1% surface-mount termina-
tion resistors.
A point-to-point interface terminated at each end in the
characteristic impedance of the cable or PCB traces is
shown in Figure 10. The total load seen by the serializer
is 50Ω. The double termination typically reduces reflec-
tions compared to a single 100Ω termination. A single
100Ω termination at the deserializer input is feasible
and makes the differential signal swing larger.
A point-to-point version of a multidrop bus is shown in
Figure 11. The low-jitter MAX9150 10-port repeater is
used to reproduce and transmit the serializer output
over 10 double-terminated point-to-point links.
Compared to a bus, more interconnect is traded for
robust hot-plug capability.
The repeater eliminates nine serializers compared to 10
individual point-to-point serializer-to-deserializer con-
nections. Since repeater jitter is a component of the
total jitter seen at the deserializer input (along with
other sources of jitter), a low-jitter repeater is essential
in most high data-rate applications.
A four-layer PCB providing separate power, ground,
and signal layers is recommended. Keep the
LVTTL/LVCMOS inputs and outputs separated from the
BLVDS inputs to prevent coupling into the BLVDS lines.
PROCESS: CMOS
REN
High
Low
X
LOGIC INPUTS
PWRDN
High
High
______________________________________________________________________________________
Low
Chip Information
Power applied and stable
Deserializer initialized
Deserializer initialized
CONDITIONS
Board Layout
Topologies
10-Bit Bus LVDS Deserializers
Power-down mode. PLL is stopped. Current consumption is reduced
to 400μA (typ). ROUT_, RCLK, and LOCK are high impedance.
RCLK and ROUT_ are high impedance. LOCK is active, indicating
the serial input status.
RCLK and ROUT_ are active. LOCK is active, indicating the serial
input status.
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
28 SSOP
TYPE
TOP VIEW
RCLK_R/F
REFCLK
PWRDN
AGND
AGND
AGND
DGND
AVCC
AVCC
RCLK
LOCK
REN
RI+
RI-
PACKAGE
A28+4
CODE
OUTPUTS
10
11
12
13
14
1
2
3
4
5
6
7
8
9
Package Information
+
MAX9206/
MAX9208
SSOP
Pin Configuration
OUTLINE
21-0056
NO.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ROUT0
ROUT1
ROUT2
ROUT3
ROUT4
DVCC
DGND
DVCC
DGND
ROUT5
ROUT6
ROUT7
ROUT8
ROUT9
PATTERN NO.
90-0095
LAND
11

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