PI2EQX5804CNJE Pericom Semiconductor, PI2EQX5804CNJE Datasheet - Page 13

• Manufacturer Part Number: PI2EQX5804CNJE
• Description: IC PCI-E REDRIVER 100LBGA
• Manufacturer: Pericom Semiconductor
• Series: ReDriver™r
• Type: Redriverr

Specifications of PI2EQX5804CNJE

• Tx/rx Type: CML
• Capacitance - Input: 50pF
• Voltage - Supply: 1.15 V ~ 1.25 V
• Current - Supply: 800mA
• Mounting Type: Surface Mount
• Package / Case: 100-LBGA
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Delay Time: -
• Lead Free Status / Rohs Status: Details

BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently.
When and INDIS_xy bit is logic 1, then the input buffer is switched off and the input termination is high im-
pedance. This feature can be used for PCB testing, and when only one input is used during Loopback as a de-
mux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently.
When and OUTDIS_xy bit is logic 1, then the output buffer is switched off and the termination is high imped-
ance. This feature can be used for PCB testing, and when only one output is used during Loopback as a mux
function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RESET# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefi ned, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition
from 0 to 1 initiates a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled).
While static at 0 or 1, the RES_zy# bit will have no effect on operation. The Channel Reset bits are read/write
allowing the current state to be checked.
Power-on
Power-on
Power-on
Name
Name
Name
Type
State
Type
State
Type
State
Bit
Bit
Bit
09-0001
INDIS_A0
ODIS_A0
RES_A0#
RESET#
R/W
R/W
R/W
7
0
7
0
7
INDIS_B0
ODIS_B0
RES_B0#
RESET#
R/W
R/W
R/W
6
0
6
0
6
INDIS_A1
ODIS_A1
RES_A1#
RESET#
R/W
R/W
R/W
5
0
5
0
5
INDIS_B1
ODIS_B1
RES_B1#
RESET#
R/W
R/W
R/W
13
4
0
4
0
4
INDIS_A2
ODIS_A2
RES_A2#
RESET#
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with
R/W
R/W
R/W
3
0
3
0
3
INDIS_B2
ODIS_B2
RES_B2#
RESET#
R/W
R/W
R/W
2
0
2
0
2
Equalization & Emphasis
INDIS_A3
ODIS_A3
RES_A3#
RESET#
R/W
R/W
R/W
1
0
1
0
1
PS8926B
PI2EQX5804C
INDIS_B3
ODIS_B3
RES_B3#
RESET#
R/W
R/W
R/W
0
0
0
0
0
06/08/09