PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet
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PI7C9X7952 PCI Express® Dual UART Datasheet Revision 1.3 September 2009 Telephone: 1-877-PERICOM, (1-877-737-4266) 09-0087 3545 North 1ST Street, San Jose, CA 95134 FAX: 408-435-1100 Internet: http://www.pericom.com ...
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... Pericom Semiconductor does not assume any responsibility for use of any circuitry described other than the circuitry embodied in a Pericom Semiconductor product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use ...
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... September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 Description Preliminary Datasheet Fixed the diagrams Corrected Chapter 4.2 Pin Description (RREF, GPIO[7]) Updated Chapter 6 PCI Express Registers(6.2.42 [3], 6.2.36 UART Driver Setting, 6.2.41 GPIO Control Register ) Revised Chapter 7 ...
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... BASE ADDRESS REGISTER 0 – OFFSET 10h.....................................................................27 6.2.11. BASE ADDRESS REGISTER 1 – OFFSET 14h.....................................................................27 6.2.12. SUBSYSTEM VENDOR REGISTER – OFFSET 2Ch ............................................................27 6.2.13. SUBSYSTEM ID REGISTER – OFFSET 2Ch........................................................................27 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page PI7C9X7952 Datasheet ...
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... CORRECTABLE ERROR MASK REGISTER – OFFSET 114h .............................................40 6.2.64. ADVANCE ERROR CAPABILITIES AND CONTROL REGISTER – OFFSET 118h.............41 6.2.65. HEADER LOG REGISTER – OFFSET From 11Ch to 128h .................................................41 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page PI7C9X7952 Datasheet ...
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... LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh ..................................................60 8. EEPROM INTERFACE .....................................................................................................................61 8.1. AUTO MODE EERPOM ACCESS ...............................................................................................61 8.2. EEPROM MODE AT RESET ........................................................................................................61 8.3. EEPROM SPACE ADDRESS MAP AND DESCRIPTION ..........................................................61 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 M .......................................................................................49 ODE Page PI7C9X7952 PCI Express® Dual UART Datasheet ...
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... ELECTRICAL SPECIFICATION.....................................................................................................63 9.1. ABSOLUTE MAXIMUM RATINGS ...........................................................................................63 9.2. DC SPECIFICATIONS..................................................................................................................63 9.3. AC SPECIFICATIONS..................................................................................................................63 10. CLOCK SCHEME ..........................................................................................................................66 11. PACKAGE INFORMATION .........................................................................................................67 12. ORDER INFORMATION ..............................................................................................................68 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page PI7C9X7952 Datasheet ...
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... F 5 IGURE XTERNAL LOCK OURCE AS THE F 7-1 UART IGURE EGISTER LOCK F 7-2 UART IGURE EGISTER LOCK F 11-1 P IGURE ACKAGE OUTLINE DRAWING September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 ................................................................................................23 ETTING .......................................................................................................23 .............................................................................................42 ODE M ....................................................................................49 EMORY ODE .....................................................................................................63 ..............................................................................................63 .................................................................................................63 .......................................................................................................64 ....................................................................................................66 ...................................................................................................10 .................................................................................................. ...........................................................................22 LOCK OURCE C S ....................................................................22 ...
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... Multi-port RS-232/ RS-422/ RS-485 Cards Point-of-Sale Systems (PoS) Industrial PC (IPC) Industrial Control Gaming Machines Building Automation Embedded Systems September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 Page PI7C9X7952 PCI Express® Dual UART Datasheet ...
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... CLKINN RREF SR_DI EEPROM SR_CS Interface SR_DO SR_CLK_O Reference XTLO Clock XTLI Figure 3-1 PI7C9X7952 Block Diagram September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART SOUT[1:0] Interrupt SIN[1:0] Interface DCD[1:0] DTR[1:0] RTS[1:0] CTS[1:0] Dual DSR[1:0] UART ...
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... VSS 56 DRIVER_SEL1[1]/DTX[2] 25 VDDCAUX 57 DRIVER_SEL1[2]/DTX[3] 26 RXP 58 DRIVER_SEL1[3]/DEQ[0] 27 VSS RXN RREF VDDA VSS 63 VDDR 32 VDDA 64 VSS September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PIN NAME VDDC 70 VSS 71 SOUT[0] 72 RTS[0]/EEPROM_BYPASS 73 DTR[0] 74 SIN[0] 75 CTS[0] 76 DSR[0] 77 RI[0] 78 DCD[0] 79 SOUT[1] 80 RTS[1] 81 DTR[1] ...
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... XTLI *52, *51, 50, DRIVER_SEL0 *49 [3:0] September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION O UART Serial Data Outputs: The output pins transmit serial data packets with start and end bits. SOUT[0] and SOUT[1] are output signals with weak internal pull-down resistors. ...
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... RREF 4.2.3. SYSTEM INTERFACE PIN NO. NAME 36 PEREST_L September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION O DRIVER_SEL1: Used to select RS-232/ RS-424/ 4-Wire RS-485/ 2-Wire RS-458 Serial Port Mode for UART 1. Driver Equalization Level Control (DEQ[0]): During system initialization, DRIVER_SEL1[3] acts as the DEQ[0] pin, and it is used to control the driver current level. By default set to ‘ ...
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... JTG_TCK 110 JTG_TRST_L 5 SCAN_EN 37 TEST September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION I/O General-Purpose Bi-Direction Signals / SR_ORG: These eight general-purpose pins are programmed as either input-only or bi-directional pins by writing the GPIO output enable control register. GPIO[ bi-directional signal with a weak internal pull-up resistor, and other GPIO pins are bi-directional signals with weak internal pull-down resistors ...
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... VTT 3, 4, 13, 15, VSS 19, 24, 27, 31, 35, 42, 54, 64, 70, 96, 100, 101, 117, 118 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION These pins can be left floating. TYPE DESCRIPTION O EEPROM Chip Select: SR_CS is an output signal with a weak internal pull-up resistor. ...
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... UART’s transmit and receive data FIFOs can be conveniently accessed by reading and writing the registers in the UART configuration space. These registers allow flexible programming capability and versatile device operations of the PI7C9X7952. Each UART is accessed through an 8-byte I/O blocks. The addresses September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page ...
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... I/O Base Address Registers, the transaction is recognized as an I/O Read or Write. 5.2.3. Memory Reads/Writes Similar to the I/O Read/Write, if the address of the transaction packet is within the memory range, a Memory Read/Write occurs. September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page PI7C9X7952 Datasheet ...
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... The data that arrive most recently are written to the bottom of the THR. If the THR is full, and the user attempts to write data to the THR, a data overrun occurs and the data is lost. September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 EFR[4] ...
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... Counter (RFDC) and Transmit FIFO Data Counter (TFDC) registers to determine the number of items in each FIFO. RHR WP RP DATA125 DATA126 DATA127 Figure 5-1 Transmit and Receive FIFOs September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI EXPRESS MASTER UART COMMON MODE ADDRESS LSR THR DATA0 DATA0 LSR0 ...
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... The UART deasserts RTS# to signal the remote transmitter that the local receive FIFO reaches the programmed upper trigger level. When the local receive FIFO falls below the programmed lower trigger level, the RTS# is reasserted. The automatic out-of-band flow control is enabled by EFR[7:6]. September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page ...
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... This feature provides the users a way to perform system diagnostics by allowing the UART to receive the same data it is sending. Figure 5-2 Internal Loopback in PI7C9X7952 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART VCC ...
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... When a crystal oscillator is used, the XTLI is the input and XTLO is the output, and the crystal should be connected in parallel with two capacitors. Figure 5-3 Crystal Oscillator as the Clock Source VCC GND Figure 5-4 External Clock Source as the Clock Source September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 XTLI R XTLO 14.7456 MHz C1 ...
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... Power Management The PI7C9X7952 supports the D0, D1, D2 and D3 power states. The device is compliant with PCI Power Management Specification Revision 1.2. September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 ency escaler 1 SampleCloc (SCR = ‘0h’ to ‘Ch’) ...
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... Link Status Next Capability Capability Version Offset = 000h Uncorrectable Error Status Register Uncorrectable Error Mask Register Uncorrectable Error Severity Register September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 DEFINITION Hardware Initialization Read Only Write Only Read / Write Read / Write 1 to Clear ...
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... Reserved 6.2.4. STATUS REGISTER – OFFSET 04h BIT FUNCTION 18:16 Reserved 19 Interrupt Status September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 23 – – 8 Correctable Error Mask Register Header Log Register TYPE DESCRIPTION RO Identifies Pericom as the vendor of this device. The register is hardwired as 12D8h. ...
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... Cache Line Size 6.2.8. MASTER LATENCY TIMER REGISTER – OFFSET 0Ch BIT FUNCTION 15:8 Latency timer September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION Reset to 0b. Set enable support for the capability list (offset 34h is the pointer to the data structure) RO Reset to 1b ...
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... FUNCTION 7:0 Capabilities Pointer 6.2.15. INTERRUPT LINE REGISTER – OFFSET 3Ch BIT FUNCTION 7:0 Interrupt Line September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION Read as 00h to indicate that the register layout conforms to the RO standard PCI-to-PCI bridge layout. TYPE DESCRIPTION Use this I/O base address to map the UART 16550 compatible registers ...
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... POWER MANAGEMENT DATA REGISTER – OFFSET 84h BIT FUNCTION 1:0 Power State 2 Reserved 3 No_Soft_Reset September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION Identifies the legacy interrupt Message(s) the device uses. RO Reset to 01h. TYPE DESCRIPTION Read as 01h to indicate that these are power management enhanced RO capability registers ...
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... FUNCTION 1:0 Reserved 31:2 Message Address 6.2.26. MESSAGE UPPER ADDRESS REGISTER – OFFSET 94h September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION auto-loading from EEPROM. Reset to 0b. RO Read as 0h. When asserted, the I/O bridge will generate the PME# message. ...
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... VPD Data 6.2.32. VENDOR SPECIFIC CAPABILITY ID REGISTER – OFFSET A4h BIT FUNCTION Enhanced 7:0 Capabilities ID September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION This register is only effective if the device supports a 64-bit message address is set. RW Reset to 00000000h. TYPE DESCRIPTION RW Reset to 0000h ...
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... Reserved 6.2.39. UART DRIVE SETTING – OFFSET B4h BIT FUNCTION UART 0 3:0 Transmitter Driver Enable September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION The pointer points to the PCI Express capability register (E0h). RO Reset to E0h. TYPE DESCRIPTION The length field provides the information for number of bytes in the capability structure (including the ID and Next pointer bytes) ...
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... High Driver Current Driver Transmit 5:2 Current De-emphasis 9:6 Transmit Equalization September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION 0000b: RS232 0001b: RS422 1011b: RS485-4W 1111b: RS485-2W Reset to 0000b. UART 1 DRIVER. The default value may be changed by auto-loading from EEPROM. ...
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... Capabilities ID 6.2.48. NEXT ITEM POINTER REGISTER – OFFSET E0h BIT FUNCTION 15:8 Next Item Pointer September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION It indicates the status of the strapping pins RXTRMADJ[1:0]. The HwInt default value may be changed by auto-loading from EEPROM. ...
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... Limit Scale 31:28 Reserved 6.2.51. DEVICE CONTROL REGISTER – OFFSET E8h BIT FUNCTION September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION Read as 0001b to indicate the I/O bridge is compliant to Revision RO 1.0a of PCI Express Base Specifications. Indicates the type of Legacy PCI Express Endpoint device. ...
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... Correctable Error 16 Detected Non-Fatal Error 17 Detected 18 Fatal Error Detected Unsupported 19 Request Detected September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION 0b: Disable Correctable Error Reporting. 1b: Enable Correctable Error Reporting. RW Reset to 0b. 0b: Disable Non-Fatal Error Reporting. 1b: Enable Non-Fatal Error Reporting. RW Reset to 0b. ...
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... Reserved Read Completion 3 Boundary (RCB) 4 Link Disable 5 Retrain Link Common Clock 6 Configuration September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION Asserted when the AUX power is detected by the I/O bridge RO Reset to 1b not implemented. Hardwired to 0b Reset to 000h. TYPE DESCRIPTION Indicates the Maximum Link Speed of the given PCIe Link ...
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... BIT FUNCTION Training Error 0 Status 3:1 Reserved September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION When set, it transmits 4096 FTS ordered sets in the L0s state for entering L0 state and transmits 1024 TS1 ordered sets in the L1 state RW for entering L0 state Reset to 0b ...
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... Poisoned TLP Mask Flow Control 13 Protocol Error Mask Completion 14 Timeout Mask September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION When set, indicates that the Data Link Protocol Error event has occurred. RW1CS Reset to 0b. RO Reset to 0000000b. When set, indicates that a Poisoned TLP has been received or generated ...
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... Completer Abort 15 Severity Unexpected 16 Completion Severity September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION When set, the Completer Abort event is not logged in the Header Log register and not issued as an Error Message to RC either. RWS Reset to 0b. When set, the Unexpected Completion event is not logged in the Header Log register and not issued as an Error Message to RC either ...
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... CORRECTABLE ERROR MASK REGISTER – OFFSET 114h BIT FUNCTION 0 Receiver Error Mask 5:1 Reserved 6 Bad TLP Mask 7 Bad DLLP Mask REPLAY_NUM 8 Rollover Mask September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION 0b: Non-Fatal. 1b: Fatal. RWS Reset to 1b. 0b: Non-Fatal. 1b: Fatal. RWS Reset to 1b. 0b: Non-Fatal. 1b: Fatal. RWS Reset to 0b ...
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... DWORD rd 11:8 3 DWORD th 15:12 4 DWORD September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RO Reset to 000b. When set, the Replay Timer Timeout event is not logged in the Header Log register and not issued as an Error Message to RC either. RWS Reset to 0b. ...
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... Figure 7-1 UART Register Block Arrangement in I/O Mode Table 7-1 UART Base Address in I/O Mode UART UART I/O Base Address UART0 BAR0 + 000h UART1 BAR0 + 008h September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 000h UART0 Registers 008h UART1 Registers Page PI7C9X7952 PCI Express® Dual UART ...
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... Tx Empty Interrupt 2 Rx Status Interrupt 3 Modem Status Interrupt 4 Xoff/Special character interrupt September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 Register Name Receive Holding Register Transmit Holding Register Interrupt Enable Register Interrupt Status Register FIFO Control Register Line Control Register Modem Control Register ...
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... Rx FIFO Flush 2 Tx FIFO Flush 3 Reserved 5:4 Tx Trigger Level 7:6 Rx Trigger Level September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RW 0b: Disable RTS/DTR Interrupt 1b: Enable RTS/DTR Interrupt Reset to 0b. RW 0b: Disable CTS/DSR interrupt 1b: Enable CTS/DSR interrupt Reset to 0b. ...
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... DTR Pin Control 1 RTS Pin Control 2 Output 1 3 Output 2 4 Internal Loopback Mode September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RW 00b: 5-bit data length 01b: 6-bit data length 10b: 7-bit data length 11b: 8-bit data length Reset to 11b. RW ...
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... Rx Frame Error 4 Rx Break Error 5 Tx Empty 6 Tx Complete September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RW Autoflow Control Enable. When the AFE is enabled, autoflow control is enabled. When it is disabled, the diagnostic mode is enabled. In the diagnostic mode, transmitted data is immediately received. When AFE is set to “ ...
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... Force Transmission 1 Auto DSR and DTR Flow Control 2 Reserved 3 Reserved 4 Reserved September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RO 0b FIFO error 1b: Rx FIFO error Reset to 0b. TYPE DESCRIPTION RO 0b: No change in CTS input. 1b: Indicates the CTS input has changed state. ...
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... Divisor High 7.1.13. SAMPLE CLOCK REGISTER – OFFSET 02h, LCR[ BIT FUNCTION 3:0 Sample Clock 7:4 Reserve September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RW 1b: Enables 950 mode 0b: Non-950 mode Reset to 0b. RW 1b: OFFSET 15 bit[7:0] acts as the Line Status Register Counter 0b: OFFSET 15 bit[7:0] acts as the Receive FIFO Data Counter Reset to 0b ...
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... Figure 7-2 UART Register Block Arrangement in Memory Mode Table 7-3 UART Base Address in Memory Mode UART UART I/O Base Address UART0 BAR1 + 0000h UART1 BAR1 + 0200h September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART 0000h UART0 Registers 0200h UART1 Registers Page PI7C9X7952 ...
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... UART Memory Base Address + 180h ~1FFh 7.2.1. RECEIVE HOLDING REGISTER – OFFSET 00h BIT FUNCTION 7:0 Rx Holding September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 Register Name Mnemonic Receive Holding Register Transmit Holding Register Interrupt Enable Register Interrupt Status Register FIFO Control Register ...
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... September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION WO When data are written to the Transmit Holding Register (THR), they are written to the bottom of the transmitter’s associated FIFOs, which holds a queue of data to be transmitted by the transmitter. Data written to the THR when the FIFOs are full are lost. The Line Status Register (LSR) indicates the full or empty status of the FIFOs ...
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... Rx FIFO Flush 2 Tx FIFO Flush 3 Reserved 5:4 Tx Trigger Level 7:6 Rx Trigger Level 7.2.6. LINE CONTROL REGISTER – OFFSET 03h BIT FUNCTION 1:0 Data Length 2 Stop-Bit Length 5:3 Parity Type September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION WO 0b: Disable the FIFO mode 1b: Enable the FIFO mode Reset to 0b ...
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... Internal Loopback Mode 5 AFE 6 Reserved 7 Enhanced Transmission September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RW 0b: No transmit break condition 1b: Force the transmitter output to a space for alerting the remote receiver of a line break condition. Reset to 0b. RW 0b: Data registers are selected 1b: Divisor latch registers are selected Reset to 0b ...
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... BIT FUNCTION 0 Delta CTS 1 Delta DSR 2 Delta RI 3 Delta DCD 4 CTS September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RO 0b: No data in the receive FIFO 1b: Data in the receive FIFO Reset to 0b. RO 0b: No overrun error 1b: Overrun error Reset to 0b. RO 0b: No parity error 1b: Parity error Reset to 0b ...
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... ENHANCED FUNCTION REGISTER – OFFSET 0Ah BIT FUNCTION 1:0 In-Band Receive Flow Control Mode September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RO 0b: The DSR input state is the logic 0 1b: The DSR input state is the logic 1 Reset to 0b. ...
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... Flow Control Enable 7 Automatic CTS Flow Control Enable September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION character(s). When this occurs, the UART will disable transmission as soon as any current character transmission is complete. The UART then compares the received data with the programmed XON character(s) ...
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... XOFF2 7.2.18. ADVANCE CONTROL REGISTER – OFFSET 0Fh BIT FUNCTION 0 Transmitter Terminate Condition 1 Remote TX Disable 2 Xon/Xoff Detect September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION Reset to 0b. TYPE DESCRIPTION RW Xon character 1. Reset to 00h. TYPE DESCRIPTION RW Xon character 2. Reset to 00h. ...
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... RECEIVE FIFO DATA COUNTER – OFFSET 15h, SFR[ The function of this register is selected by the Special Function Register (Offset 07h) bit 6. When SFR[6] is set to ‘1’, this register functions as the Receive FIFO Data Counter. Otherwise, it functions as the Line September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION ...
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... GLOBAL LINE STATUS REGISTER – OFFSET 17h BIT FUNCTION 0 RX Data Available 1 RX FIFO Overrun September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RO The Receive FIFO Data Counter indicates the amount of data in the Receive FIFO. Reset to 00h. TYPE ...
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... FUNCTION 7:0 Transmit FIFO Data 7.2.31. LINE STATUS FIFO REGISTERS –OFFSET 180h ~ 1FFh BIT FUNCTION 7:0 Line Status FIFO September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 TYPE DESCRIPTION RO 0b: No parity error 1b: Parity error Reset to 0b. RO 0b: No framing error 1b: Framing error Reset to 0b ...
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... Offset B0h bit [31:16] 10h Bit[1:0] - Offset ECh bit[11:10] Bit[4:2] - Offset ECh bit[14:12] Bit[7:5] - Offset ECh bit[17:15] 12h Offset B4h bit[15:0] September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART DEFAULT DESCRIPTION Value A868h Check Code 12D8h ...
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... Bit[13:0] - Offset C8h bit[13:0] 1Ah Bit[0] - Offset C4h bit[15] Bit[15:8] - Offset 34h bit[7:0] 1Ch [7:0] - Offset 08h bit[7:0] 40h September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART DEFAULT DESCRIPTION Value 0000h UART Transmitter Drive Enable: RS232/422/485-2W/485-4W Selection for UART 4 ...
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... TX-CM-AC V Transmit common-mode voltage in L0s TX-CM-HiZ (TX) & De-emphasized differential output TX-DE-RATIO voltage V Electric Idle differential peak voltage TX-IDLE-DIFFp September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Typ. Max. 1.8v 2.0v 1.8v 2.0v 1.8v 2.0v VDDC 2.0v 3 ...
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... Maximum time between jitter RX-EYE-MEDIAN-to-MAX-JITTER median and max deviation from median Timing Parameters LRLAT-10 Receiver data latency for n=10 LRLAT-20 Receiver data latency for n=20 September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Min Typical V TX-DIFFp ...
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... Over a frequency range of 50 MHz to 1.25 GHz. b. Over a frequency range of 50 MHz to 1.25 GHz. c. Assuming synchronized bit streams at the respective receiver inputs. d. This is a function of beacon frequency September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Min Typical ...
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... Duty cycle of input clock Rise/Fall time of input clock Differential input voltage swing SW a. RCUI (Reference Clock Unit Interval) refers to the reference clock period September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Min Typical - 100 (zero-to-peak) 0.4 ...
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... PACKAGE INFORMATION The package of PI7C9X7952 is a 14mm x 14mm LQFP (128 Pin) package. The following are the package information and mechanical dimension: Figure 11-1 Package outline drawing September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 PCI Express® Dual UART Page PI7C9X7952 ...
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... Order Information Part Number Temperature Range o □ - PI7C9X7952 FDE (Industrial Temperature 9X7952 FD E September 2009 – Revision 1.3 Pericom Semiconductor 09-0087 Package o C 128-pin LQFP 14mm x 14mm Blank=Standard E=Pb-Free and Green Package Code Blank=Standard =Revision Device Type Device Number Family PI=Pericom ...