PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 25

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.1.
6.2.2.
6.2.3.
6.2.4.
September 2009 – Revision 1.3
Pericom Semiconductor
VENDOR ID REGISTER – OFFSET 00h
DEVICE ID REGISTER – OFFSET 00h
COMMAND REGISTER – OFFSET 04h
STATUS REGISTER – OFFSET 04h
BIT
15:0
BIT
31:16
BIT
0
1
2
3
4
5
6
7
8
9
10
15:11
BIT
18:16
19
31 – 24
FUNCTION
Vendor ID
FUNCTION
Device ID
FUNCTION
I/O Space Enable
Memory Space
Enable
Bus Master Enable
Special Cycle
Enable
Memory Write And
Invalidate Enable
VGA Palette Snoop
Enable
Parity Error
Response Enable
Wait Cycle Control
SERR# enable
Fast Back-to-Back
Enable
Interrupt Disable
Reserved
FUNCTION
Reserved
Interrupt Status
Advanced Error Capabilities and Control Register
09-0087
Correctable Error Mask Register
23 – 16
Header Log Register
TYPE
TYPE
TYPE
TYPE
RO
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
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DESCRIPTION
Identifies Pericom as the vendor of this device. The register is
hardwired as 12D8h.
DESCRIPTION
Identifies this device as the PI7C9X7952. Reset to 7952h.
DESCRIPTION
Controls a device’s response to I/O Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
respond to I/O Space accesses.
Reset to 0b.
Controls a device’s response to Memory Space accesses. A value of 0
disables the device response. A value of 1 allows the device to
response to memory Space accesses.
Reset to 0b.
It is not implemented. Hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Controls the device’s response to parity errors. When the bit is set,
the device must take its normal action when a parity error is
detected. When the bit is 0, the device sets its Detected Parity Error
Status bit when an error is detected.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
This bit, when set, enables reporting of Non-fatal and Fatal errors
detected by the device to the Root Complex.
Reset to 0b.
Does not apply to PCI Express. Must be hardwired to 0b.
Controls the ability of the I/O bridge to generate INTx interrupt
Messages.
Reset to 0b.
Reset to 00000b.
DESCRIPTION
Reset to 000b.
Indicates that an INTx interrupt Message is pending internally to the
device.
15 – 8
7 – 0
PCI Express® Dual UART
BYTE OFFSET
11Ch~128h
114h
118h
PI7C9X7952
Datasheet