PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 18

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.2.4.
All of the internal UART channels in the I/O Bridge support the 16C450, 16C550, Enhanced 16C550, and
Enhanced 950 UART Modes. The mode of the UART operation is selected by toggling the Special Function
Register (SFR[5]) and Enhanced Function Register (EFR[4]). The FIFO depth of each mode and the mode
selection is tabulated in the table below.
5.2.5.
The 450 Mode is inherently supported when 550 Mode is selected. When in the 450 Mode, the FIFOs are in
the “Byte Mode”, which refers to the one-byte buffer in the Transmit Holding Register and the Receive
Holding Register in each of the UART channels. When in the 550 Mode, the UARTs support an increased
FIFO depth of 16.
When EFR[4] is set to “0”, the SFR[5] is ignored, and the 450/550 Mode is selected.
5.2.6.
Setting the SFR[5] to “0” and EFR[4] to “1” enables the Enhanced 550 Mode. The Enhanced 550 Mode
further increases FIFO depth to 128.
5.2.7.
128-deep FIFOs are supported in the Enhanced 950 Mode. When the Enhanced 950 Mode is enabled, the
UART channels support additional features:








5.2.8.
Each channel of the UARTs consists of 128 bytes of transmit FIFOs and 128 bytes of receive FIFOs,
namely the Transmit Holding Registers (THR) and the Receive Holding Registers (RHR). The FIFOs
provide storage space for the data before they can be transmitted or processed. The THR and RHR operate
simultaneously to transmit and read data.
The transmitter reads data from the THR into the Transmit Shift Register (TSR) and removes the data from
top of the THR. It then converts the data into serial format with start and stop bits and parity bits if required.
If the transmitter completes transmitting the data in the TSR and the THR is empty, the transmitter is in the
idle state. The data that arrive most recently are written to the bottom of the THR. If the THR is full, and
the user attempts to write data to the THR, a data overrun occurs and the data is lost.
September 2009 – Revision 1.3
Pericom Semiconductor
Sleep mode
Special character detection
Automatic in-band flow control
Automatic flow control using selectable arbitrary thresholds
Readable status for automatic in-band and out-of-band flow control
Flexible clock prescaler
Programmable sample clock
DSR/DTR automatic flow control
UART Mode
450/550
Enhanced 550
Enhanced 950
Mode Selection
450/550 Mode
Enhanced 550 Mode
Enhanced 950 Mode
Transmit and Receive FIFOs
Table 5-1 Mode Selection
SFR[5]
X
0
1
09-0087
EFR[4]
0
1
1
Page 18 of 68
FIFO Size
1/16
128
128
PCI Express® Dual UART
PI7C9X7952
Datasheet