PI7C9X7952AFDE Pericom Semiconductor, PI7C9X7952AFDE Datasheet - Page 28

• Manufacturer Part Number: PI7C9X7952AFDE
• Description: IC PCIE-TO-UART BRIDGE 128LQFP
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X7952AFDE

• Applications: PCIe-to-Uart Bridge
• Interface: Advanced Configuration Power Interface (ACPI)
• Voltage - Supply: 1.8V, 3.3V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.2.16. INTERRUPT PIN REGISTER – OFFSET 3Ch
6.2.17. POWER MANAGEMENT CAPABILITY ID REGISTER – OFFSET 80h
6.2.18. NEXT ITEM POINTER REGISTER – OFFSET 80h
6.2.19. POWER MANAGEMENT CAPABILITIES REGISTER – OFFSET 80h
6.2.20. POWER MANAGEMENT DATA REGISTER – OFFSET 84h
September 2009 – Revision 1.3
Pericom Semiconductor
BIT
15:8
BIT
7:0
BIT
15:8
BIT
18:16
19
20
21
24:22
25
26
31:27
BIT
1:0
2
3
FUNCTION
Enhanced
Capabilities ID
Next Item Pointer
FUNCTION
Interrupt Pin
FUNCTION
FUNCTION
Power Management
Revision
PME# Clock
Auxiliary Power
Device Specific
Initialization
AUX Current
D1 Power State
Support
D2 Power State
Support
PME# Support
FUNCTION
Power State
Reserved
No_Soft_Reset
09-0087
TYPE
TYPE
TYPE
TYPE
TYPE
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RO
RO
Page 28 of 68
DESCRIPTION
Read as 01h to indicate that these are power management enhanced
capability registers.
DESCRIPTION
Identifies the legacy interrupt Message(s) the device uses.
Reset to 01h.
DESCRIPTION
The pointer points to the Power Management capability register
(8Ch).
Reset to 8Ch.
DESCRIPTION
Read as 011b to indicate the I/O bridge is compliant to Revision 1.1
of PCI Power Management Interface Specifications.
Does not apply to PCI Express. Must be hardwired to 0b.
Read as 1b to indicate the I/O bridge forwards the PME# message in
D3cold and an auxiliary power source is required.
Read as 0b to indicate the I/O bridge does not have device specific
initialization requirements. The default value may be changed by
auto-loading from EEPROM.
Reset as 111b to indicate the I/O bridge need 375 mA in D3 state.
The default value may be changed by auto-loading from EEPROM.
Read as 1b to indicate the I/O bridge supports the D1 power
management state. The default value may be changed by
auto-loading from EEPROM.
Read as 1b to indicate the I/O bridge supports the D2 power
management state. The default value may be changed by
auto-loading from EEPROM.
Read as 01000b to indicate the I/O bridge supports the forwarding of
PME# message in all power states. The default value may be
changed by auto-loading from EEPROM.
DESCRIPTION
Indicates the current power state of the I/O bridge. Writing a value of
D0 causes a hot reset without asserting PEREST_L when the
previous state was D3.
00b: D0 state
01b: D1 state
10b: D2 state
11b: D3 hot state
Reset to 00b.
Read as 0b.
When set, this bit indicates that I/O bridge transitioning from D3hot
to D0 does not perform an internal reset.
When clear, an internal reset is performed when power state transits
from D3hot to D0. The default value may be changed by
PCI Express® Dual UART
PI7C9X7952
Datasheet