PI7C9X20303ULAZPE Pericom Semiconductor, PI7C9X20303ULAZPE Datasheet - Page 11

• Manufacturer Part Number: PI7C9X20303ULAZPE
• Description: IC PCIE PACKET SWITCH 132VQFN
• Manufacturer: Pericom Semiconductor
• Series: UltraLo™r

Specifications of PI7C9X20303ULAZPE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 132-VQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

PI7C9X20303UL
3Port-3Lane PCI Express® Switch
TM
UltraLo
Family
Datasheet
2
GENERAL DESCRIPTION
Similar to the role of PCI/PCIX Bridge in PCI/PCIX bus architecture, the function of PCI Express (PCIE) Switch is
to expand the connectivity to allow more end devices to be reached by host controllers in PCIE serial interconnect
architecture. The 3-lane PCIE Switch can be configured as 3-port type combinations. It provides users the flexibility
to expand or fan-out the PCI Express lanes based on their application needs. For some systems that do not need all
the 3 lanes, the unused lanes can be disabled to reduce power consumption.
In the PCI Express Architecture, the PCIE Switch forwards posted and non-posted requests and completion packets
in either downstream or upstream direction concurrently as if a virtual PCI Bridge is in operation on each port. By
visualizing the port as a virtual Bridge, the Switch can be logically viewed as two-level cascaded multiple virtual
PCI-to-PCI Bridges, where one upstream-port Bridge sits on all downstream-port Bridges. Similar to a PCI Bridge
during enumeration, each port is given a unique bus number, device number, and function number by the initiating
software. The bus number, device number, and function number are combined to form a destination ID for each
specific port. In addition to that, the memory-map and IO address ranges are exclusively allocated to each port as
well. After the software enumeration is finished, the packets are routed to the dedicated port based on the embedded
address or destination ID. To ensure the packet integrity during forwarding, the Switch is not allowed to split the
packets to multiple small packets or merge the received packets into a large transmit packet. Also, the IDs of the
requesters and completers are kept unchanged along the path between ingress and egress port.
The Switch employs the architecture of Combined Input and Output Queue (CIOQ) in implementation. The main
reason for choosing CIOQ is that the required memory bandwidth of input queue equals to the bandwidth of ingress
port rather than increasing proportionally with port numbers as an output queue Switch does. The CIOQ at each
ingress port contains separate dedicated queues to store packets. The packets are arbitrated to the egress port based
on the PCIe transaction-ordering rule. For the packets without ordering information, they are permitted to pass over
each other in case that the addressed egress port is available to accept them. As to the packets required to follow the
ordering rule, the Head-Of-Line (HOL) issue becomes unavoidable for packets destined to different egress ports
since the operation of producer-consumer model has to be retained; otherwise the system might occur hang-up
problem. On the other hand, the Switch places replay buffer at each egress port to defer the packets before sending it
out. This can assure the maximum throughput being achieved and therefore the Switch works efficiently. Another
advantage of implementing CIOQ in PCIe Switch is that the credit announcement to the counterpart is simplified
and streamlined because of the credit-based flow control protocol. The protocol requires that each ingress port
maintains the credits independently without checking other ports' credit availability, which is otherwise required by
pure output queue architecture.
Page 11 of 77
August 2009 – Revision 1.1
Pericom Semiconductor