PI7C9X20303ULAZPE Pericom Semiconductor, PI7C9X20303ULAZPE Datasheet - Page 26

• Manufacturer Part Number: PI7C9X20303ULAZPE
• Description: IC PCIE PACKET SWITCH 132VQFN
• Manufacturer: Pericom Semiconductor
• Series: UltraLo™r

Specifications of PI7C9X20303ULAZPE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 132-VQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

August 2009 – Revision 1.1
Pericom Semiconductor
ADDRESS
22h
24h
32h
34h
42h
44h
50h
51h
PCI CFG OFFSET
E0h (Port1)
E0h: Bit [24]
F0h (Port 1)
F0h: Bit [28]
80h (Port 1)
80h: Bit[21]
ECh (Port 1)
ECh: Bit [25:24]
84h (Port 1)
84h: Bit [14:13]
154h (Port 1)
154h: Bit [7:1]
E0h (Port 2)
E0h: Bit [24]
F0h (Port 2)
F0h: Bit [28]
80h (Port 2)
80h: Bit[21]
ECh (Port 2)
ECh: Bit [25:24]
84h (Port 2)
84h: Bit [14:13]
154h (Port 2)
154h: Bit [7:1]
F4h (Port 1)
F4h: Bit [15:0]
F4h (Port 2)
F4h: Bit [15:0]
F4h (Port 1)
F4h: Bit [31:16]
F4h (Port 2)
F4h: Bit [31:16]
84h (Port 0)
84h: Bit [3]
80h (Port 0)
80h: Bit [24:22]
80h: Bit [25]
80h: Bit [26]
80h: Bit [29:28]
84h (Port 0)
84h: Bit [31:24]
DESCRIPTION
PCIe Capability Slot Implemented for Port 1
Slot Clock Configuration for Port 1
Device specific Initialization for Port 1
Port Number for Port 1
PMCSR Data Scale for Port 1
Bit [7:6]: It represents the PMCSR Data Scale for physical port 1
VC0 TC/VC Map for Port 1
PCIe Capability Slot Implemented for Port 2
Slot Clock Configuration for Port 2
Device specific Initialization for Port 2
Port Number for Port 2
PMCSR Data Scale for Port 2
Bit [7:6]: It represents the PMCSR Data Scale for physical port 2
VC0 TC/VC Map for Port 2
Slot Capability 0 of Port 1
Slot Capability 0 of Port 2
Slot Capability 1 of Port 1
Slot Capability 1 of Port 2
No_Soft_Reset for Port 0
Power Management Capability for Port 0
Power Management Data for Port 0
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Bit [0]: When set, the slot is implemented for Port 1
Bit [1]: When set, the component uses the clock provided on the
Bit [2]: When set, the DSI is required
Bit [5:4]: It represents the logic port numbering for physical port
1
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [0]: When set, the slot is implemented for Port 2
Bit [1]: When set, the component uses the clock provided on the
Connector
Bit [2]: When set, the DSI is required
Bit [5:4]: It represents the logic port numbering for physical port
2
Bit [15:9]: When set, it indicates the corresponding TC is
mapped into VC0
Bit [15:0]: Mapping to the low word of slot capability register
Bit [15:0]: Mapping to the low word of slot capability register
Bit [15:0]: Mapping to the high word of slot capability register
Bit [15:0]: Mapping to the high word of slot capability register
Bit [0]: No_Soft_Reset.
Bit [3:1]: AUX Current.
Bit [4]: read only as 1 to indicate Bridge supports the D1 power
management state
Bit [5]: read only as 1 to indicate Bridge supports the D2 power
management state
Bit [7:6]: PME Support for D2 and D1 states
Bit [15:8]: read only as Data register
Connector
3Port-3Lane PCI Express® Switch
UltraLo
PI7C9X20303UL
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