PI7C9X20303ULAZPE Pericom Semiconductor, PI7C9X20303ULAZPE Datasheet - Page 62

• Manufacturer Part Number: PI7C9X20303ULAZPE
• Description: IC PCIE PACKET SWITCH 132VQFN
• Manufacturer: Pericom Semiconductor
• Series: UltraLo™r

Specifications of PI7C9X20303ULAZPE

• Applications: Data Transport
• Interface: Advanced Configuration Power Interface (ACPI)
• Package / Case: 132-VQFN
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -

7.2.90
7.2.91
7.2.92
August 2009 – Revision 1.1
Pericom Semiconductor
PORT VC CAPABILITY REGISTER 2 – OFFSET 148h (Upstream Only)
PORT VC CONTROL REGISTER – OFFSET 14Ch (Upstream Only)
PORT VC STATUS REGISTER – OFFSET 14Ch (Upstream Only)
BIT
6:4
7
9:8
11:10
31:12
BIT
7:0
23:8
31:24
BIT
0
3:1
15:4
BIT
16
31:17
FUNCTION
Low Priority
Extended VC Count
Reserved
Reference Clock
Port Arbitration
Table Entry Size
Reserved
FUNCTION
VC Arbitration
Capability
Reserved
VC Arbitration Table
Offset
FUNCTION
Load VC Arbitration
Table
VC Arbitration
Select
Reserved
FUNCTION
VC Arbitration Table
Status
Reserved
TYPE
TYPE
TYPE
TYPE
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Page 62 of 77
DESCRIPTION
It indicates the number of extended Virtual Channels in addition to the default
VC belonging to the low-priority VC (LPVC) group. The default value may
be changed by SMBus or auto-loading from EEPROM.
Reset to 000b.
Reset to 0b.
It indicates the reference clock for Virtual Channels that support time-based
WRR Port Arbitration. Defined encoding is 00b for 100 ns reference clock.
Reset to 00b.
Read as 10b to indicate the size of Port Arbitration table entry in the device is
4 bits.
Reset to 10b.
Reset to 0.
DESCRIPTION
It indicates the types of VC Arbitration supported by the device for the LPVC
group. This field is valid when LPVC is greater than 0. The Switch supports
Hardware fixed arbitration scheme, e.g., Round Robin and Weight Round
Robin arbitration with 32 phases in LPVC.
Reset to 00000000b.
Reset to 0.
It indicates the location of the VC Arbitration Table as an offset from the base
address of the Virtual Channel Capability register in the unit of DQWD (16
bytes).
Reset to 00h.
DESCRIPTION
When set, the programmed VC Arbitration Table is applied to the hardware.
This bit always returns 0b when read.
Reset to 0b.
This field is used to configure the VC Arbitration by selecting one of the
supported VC Arbitration schemes. The valid values for the schemes
supported by Switch are 0b and 1b. Other value than these written into this
register will be treated as default.
Reset to 0b.
Reset to 0.
DESCRIPTION
When set, it indicates that any entry of the VC Arbitration Table is written by
software. This bit is cleared when hardware finishes loading values stored in
the VC Arbitration Table after the bit of “Load VC Arbitration Table” is set.
Reset to 0b.
Reset to 0.
3Port-3Lane PCI Express® Switch
UltraLo
PI7C9X20303UL
Datasheet
TM
Family