ISP1563BMGA ST-Ericsson Inc, ISP1563BMGA Datasheet - Page 87

• Manufacturer Part Number: ISP1563BMGA
• Description: IC USB HOST CTRL HI-SPD 128LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1563BMGA

• Applications: USB Host/Function Processor
• Interface: EHCI Interface
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-LQFP
• Mounting Type: Surface Mount
• For Use With: UM10066 - EVAL BRD FOR ISP1563
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ISP1563BM-S; ISP1563BM-S

Philips Semiconductors
9397 750 14224
Product data sheet
Table 117: PORTSC 1, 2, 3, 4 - Port Status and Control, 1, 2, 3, 4 register bit
Address: Value read from func2 of address 10h + 64h + (4 × Port Number − 1) where Port Number
[1]
Bit
6
5
4
3
2
1
0
These fields read logic 0, if the PP bit is logic 0.
Symbol
FPR
OCC
OCA
PEDC
PED
ECSC
ECCS
description
Description
Force Port Resume: Logic 1 means resume detected or driven on the port.
Logic 0 means no resume (K-state) detected or driven on the port.
Default = 0. Software sets this bit to drive the resume signaling. The Host
Controller sets this bit if a J-to-K transition is detected, while the port is in the
suspend state. When this bit changes to logic 1 because a J-to-K transition is
detected, PCD (bit 2 in register USBSTS) is also set to logic 1. If software
sets this bit to logic 1, the Host Controller must not set bit PCD. When the
EHCI controller owns the port, the resume sequence follows the sequence
given in Universal Serial Bus Specification Rev. 2.0 . The resume signaling
(full-speed ‘K’) is driven on the port as long as this bit remains set. Software
must time the resume and clear this bit after the correct amount of time has
elapsed. Clearing this bit causes the port to return to high-speed mode,
forcing the bus below the port into a high-speed idle. This bit will remain at
logic 1, until the port has switched to the high-speed idle. The Host Controller
must complete this transition within 2 ms of software clearing this bit.
Overcurrent Change: Default = 0. This bit is set to logic 1 when there is a
change in overcurrent active. Software clears this bit by setting this bit to
logic 1.
Overcurrent Active: Default = 0. If set to logic 1, this port has an
overcurrent condition. If set to logic 0, this port does not have an overcurrent
condition. This bit will automatically change from logic 1 to logic 0 when the
overcurrent condition is removed.
Port Enable/Disable Change: Logic 1 means the port enabled or disabled
status has changed. Logic 0 means no change. Default = 0. For the root hub,
this bit is set only when a port is disabled because of the appropriate
conditions existing at the EOF2 point. For definition of port error, refer to
Chapter 11 of Universal Serial Bus Specification Rev. 2.0 . Software clears
this bit by setting it.
Port Enabled/Disabled: Logic 1 means enable. Logic 0 means disable.
Default = 0. Ports can only be enabled by the Host Controller as a part of the
reset and enable sequence. Software cannot enable a port by writing logic 1
to this field. The Host Controller will only set this bit when the reset sequence
determines that the attached device is a high-speed device. Ports can be
disabled by either a fault condition or by host software. The bit status does
not change until the port state has changed. There may be a delay in
disabling or enabling a port because of other Host Controller and bus events.
When the port is disabled, downstream propagation of data is blocked on this
port, except for reset.
Connect Status Change: Logic 1 means change in ECCS. Logic 0 means
no change. Default = 0. This bit indicates a change has occurred in the
ECCS of the port. The Host Controller sets this bit for all changes to the port
device connect status, even if the system software has not cleared an
existing connect status change. For example, the insertion status changes
two times before the system software has cleared the changed condition,
hub hardware will be setting an already-set bit, that is, the bit will remain set.
Software clears this bit by writing logic 1 to it.
Current Connect Status: Logic 1 indicates a device is present on port.
Logic 0 indicates no device is present. Default = 0. This value reflects the
current state of the port and may not directly correspond to the event that
caused the ECSC bit to be set.
…continued
Rev. 01 — 14 July 2005
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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
HS USB PCI Host Controller
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ISP1563
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