PDI1394L40BEUM ST-Ericsson Inc, PDI1394L40BEUM Datasheet - Page 16

• Manufacturer Part Number: PDI1394L40BEUM
• Description: IC LINK LAYER CTRLR AV 144LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of PDI1394L40BEUM

• Applications: AV,TV, VTR
• Interface: IEEE 1394
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 144-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PDI1394L40BE-T; PDI1394L40BE-T

Philips Semiconductors
12.3.2 Single capacitor isolation
The circuit example (Figure 3) shows the connections required to implement basic single capacitor Link/PHY isolation.
NOTE: The isolation enablement pins on both devices are in their “1” states, activating the bushold circuits on each part. The bushold circuits
provide local dc ground references to each side of the isolating/coupling capacitors. Also note that ground isolation/signal-coupling must be
provided in the form of a parallel combination of resistance and capacitance as indicated in the IEEE 1394 standard.
12.4 Power Management
The PDI1394L40 implements several features for power management as noted in IEEE 1394a.2000. These features include:
1. Reset of the Phy/Link interface by setting the RPL bit in the LNKCTL register.
2. Disable of the Phy/Link interface caused by either setting the SWPD bit in the RDI register –OR– asserting (high) the PD pin.
3. Initialization of the Phy/Link interface after it was disabled or reset.
The application can power up the Phy/Link interface by deasserting the PD pin –OR– clearing (low) the SWPD in the RDI register. This will
cause the L40 to produce a pulsing signal on the LPS pin. When the L40 is in power down mode, reads and writes to the host interface will be
restricted to those addressing only the RDI register (0x0B0). Please see Section 13.3.11 for further details.
There are 3 ways to power up the L40. (1) When the application wants the 1394 node to resume operation, it simply needs to de–assert the PD
pin, or (2) clear the SWPD bit in the RDI register. The link can also be awakened by another bus node sending a link–on packet to the PHY of
the application’s node. (3) The attached PHY will activate its LinkOn line and the L40 will see the signal and set the LOA bit of the RDI register.
Assuming that the ELOA bit is in its enabled, ”1”, state, the L40 will generate an interrupt of the host processor. It will then be up to the host
processor to decide whether to honor the link–on request of the other node. Then the host processor will de–assert the PD pin –OR– clear the
SWPD bit in the RDI register. This activity will power up the L40 causing it to send the pulsing signal out on the LPS pin which notifies the
PHYchip of link activity and allows the PHY to discontinue directing the link on signal to the L40. Subsequently, the host processor must
acknowledge the LOA interrupt by writing a ”1” to the LOA bit position in the RDI register after the link on signal from the PHY has stopped.
2000 Dec 15
1394 enhanced AV link layer controller
ALSO SEE APPLICATION NOTE AN2452
FOR MORE DETAILS
APPLICATION AND LINK GROUND
PDI1394L40
APPLICATION/LINK
LINK
+3.3V
Figure 3. Single capacitor Link/PHY isolation
PHYCTL0
PHYCTL1
LINKON
PHY D0
PHY D1
PHY D2
PHY D3
PHY D4
PHY D5
PHY D6
PHY D7
LREQ
SCLK
ISON
LPS
9.1K
13K
LINK
3.3V
C
C
C
C
C
C
c
c
c
c
= 1 nF; C
12
1MEG
C
C
C
C
C
C
C
r
C
C
c
c
c
c
L
= 100 nF; C
c
r
PHY
3.3V
C
C
C
C
L
c
c
c
c
= 3.3nF
ISO–
SYSCLK
D0
D1
D2
D3
D4
D5
D6
D7
PHYCTL0
PHYCTL1
LREQ
LPS
LINKON
ISOLATED/PHY
VALUES OF THESE RESISTORS DEPEND
ON PHY USED. SEE PHY DATASHEET.
+3.3V
PDI1394P2x
PHY
ISOLATED PHY GROUND
SV01836
PDI1394L40
Preliminary specification