AN983BX-BG-T-V3 Infineon Technologies, AN983BX-BG-T-V3 Datasheet - Page 54
AN983BX-BG-T-V3
Manufacturer Part Number
AN983BX-BG-T-V3
Description
IC PCI TO ETHERNET LAN 128-PQFP
Manufacturer
Infineon Technologies
Datasheet
1.AN983B-BG-T-V8.pdf
(116 pages)
Specifications of AN983BX-BG-T-V3
Applications
Ethernet Controller
Interface
USB
Voltage - Supply
3 V ~ 3.6 V
Package / Case
128-BFQFP
Mounting Type
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
AN983BXBGTV3
SP000103413
SP000103413
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AN983BX-BG-T-V3
Manufacturer:
Infineon Technologies
Quantity:
10 000
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Field
CAL
PBL
BLE
DSL
BAR
SWR
Transmit Demand Register
TDR_CSR1
Transmit Demand Register
Data Sheet
Bits
15:14
13:8
7
6:2
1
0
Type
rw*
rw*
rw*
rw*
rw*
rw*
Description
Cache Alignment, Address Boundary for Data Burst, Set after Reset
Note: rw*: Before writing the transmitting and receiving operations should
00
01
10
11
Programmable Burst Length
This value defines the maximum number of DW to be transferred in one
DMA transaction. Value: 0 (unlimited), 1, 2, 4, 8, 16 (default), 32
Note: rw*: Before writing the transmitting and receiving operations should
Big or Little Endian Selection
Note: rw*: Before writing the transmitting and receiving operations should
0
1
Descriptor Skip Length
Defines the gap between two descriptions in the units of DW.
Note: rw*: Before writing the transmitting and receiving operations should
Bus Arbitration
Note: rw*: Before writing the transmitting and receiving operations should
0
1
Software Reset
Note: rw*: Before writing the transmitting and receiving operations should
1
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
B
B
B
B
be stopped.
be stopped.
be stopped.
be stopped.
be stopped.
be stopped.
signal will be cleared by AN983B/BX itself after it completed the
reset process.
, reserved (default)
, 8 DW boundary alignment
, 16 DW boundary alignment
, 32 DW boundary alignment
, little endian (e.g. INTEL)
, big endian (only for data buffer)
, receive higher priority
, transmit higher priority
, reset all internal hardware except configuration registers. This
Offset
08
54
H
Rev. 1.81, 2005-12-15
AN983B/BX
Reset Value
FFFF FFFF
H
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