NX3L1G53GT,115 NXP Semiconductors, NX3L1G53GT,115 Datasheet

IC SWITCH SPDT 8XSON

NX3L1G53GT,115

Manufacturer Part Number
NX3L1G53GT,115
Description
IC SWITCH SPDT 8XSON
Manufacturer
NXP Semiconductors
Datasheet

Specifications of NX3L1G53GT,115

Package / Case
8-XFDFN
Function
Switch
Circuit
1 x SPDT
On-state Resistance
500 mOhm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
1.4 V ~ 4.3 V
Current - Supply
150nA
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Switch Configuration
SPDT
On Resistance (max)
1.6 Ohm (Typ) @ 1.4 V
On Time (max)
42 ns @ 1.6 V
Off Time (max)
19 ns @ 1.6 V
Supply Voltage (max)
4.3 V
Supply Voltage (min)
1.4 V
Maximum Power Dissipation
250 mW
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-4644-2
935285822115
NX3L1G53GT-G
1. General description
2. Features
The NX3L1G53 is a low-ohmic single-pole double-throw analog switch suitable for use as
an analog or digital 2:1 multiplexer/demultiplexer. It has a digital select input (S), two
independent inputs/outputs (Y0 and Y1), a common input/output (Z) and an active LOW
enable input (E). When pin E is HIGH, the switch is turned off. Schmitt-trigger action at the
digital inputs makes the circuit tolerant to slower input rise and fall times.
The NX3L1G53 allows signals with amplitude up to V
Y1; or from Y0 or Y1 to Z. Its low ON resistance (0.5 Ω) and flatness (0.13 Ω) ensures
minimal attenuation and distortion of transmitted signals.
NX3L1G53
Low-ohmic single-pole double-throw analog switch
Rev. 04 — 27 January 2010
Wide supply voltage range from 1.4 V to 4.3 V
Very low ON resistance (peak):
Break-before-make switching
High noise immunity
ESD protection:
CMOS low-power consumption
Latch-up performance exceeds 100 mA per JESD 78 Class II Level A
Direct interface with TTL levels at 3.0 V
Control input accepts voltages above supply voltage
High current handling capability (350 mA continuous current under 3.3 V supply)
Specified from −40 °C to +85 °C and from −40 °C to +125 °C
1.6 Ω (typical) at V
1.0 Ω (typical) at V
0.55 Ω (typical) at V
0.50 Ω (typical) at V
0.50 Ω (typical) at V
HBM JESD22-A114E Class 3A exceeds 7500 V
MM JESD22-A115-A exceeds 200 V
CDM AEC-Q100-011 revision B exceeds 1000 V
IEC61000-4-2 contact discharge exceeds 8000 V for switch ports
CC
CC
CC
CC
CC
= 1.4 V
= 1.65 V
= 2.3 V
= 2.7 V
= 4.3 V
CC
to be transmitted from Z to Y0 or
Product data sheet

Related parts for NX3L1G53GT,115

NX3L1G53GT,115 Summary of contents

Page 1

NX3L1G53 Low-ohmic single-pole double-throw analog switch Rev. 04 — 27 January 2010 1. General description The NX3L1G53 is a low-ohmic single-pole double-throw analog switch suitable for use as an analog or digital 2:1 multiplexer/demultiplexer. It has a digital select input ...

Page 2

... NXP Semiconductors 3. Applications Cell phone PDA Portable media player 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C NX3L1G53GT −40 °C to +125 °C NX3L1G53GD −40 °C to +125 °C NX3L1G53GM 5. Marking [1] Table 2. Marking codes Type number ...

Page 3

... NXP Semiconductors Fig 2. Logic diagram 7. Pinning information 7.1 Pinning NX3L1G53 GND 3 GND 4 Transparent top view Fig 3. Pin configuration SOT833-1 (XSON8) NX3L1G53_4 Product data sheet Low-ohmic single-pole double-throw analog switch 001aah454 Fig 4. Rev. 04 — 27 January 2010 NX3L1G53 Z 001aad387 NX3L1G53 GND 3 6 GND ...

Page 4

... NXP Semiconductors Fig 5. Pin configuration SOT902-1 (XQFN8U) 7.2 Pin description Table 3. Pin description Symbol Pin SOT833-1 and SOT996 GND 3 GND Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level don’t care. NX3L1G53_4 Product data sheet Low-ohmic single-pole double-throw analog switch ...

Page 5

... NXP Semiconductors 9. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC V input voltage I V switch voltage SW I input clamping current IK I switch clamping current SK I switch current ...

Page 6

... NXP Semiconductors 11. Static characteristics Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground 0 V). Symbol Parameter Conditions V HIGH-level input voltage LOW-level input voltage input leakage select input S and enable I current input ...

Page 7

... NXP Semiconductors 11.1 Test circuits − Fig 6. Test circuit for measuring OFF-state leakage current − Fig 7. Test circuit for measuring ON-state leakage current NX3L1G53_4 Product data sheet Low-ohmic single-pole double-throw analog switch switch GND V I − GND open circuit ...

Page 8

... NXP Semiconductors 11.2 ON resistance Table 8. ON resistance At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for graphs see Symbol Parameter R ON resistance (peak) ON(peak) ΔR ON resistance mismatch ON between channels R ON resistance (flatness) V ON(flat) [1] Typical values are measured at T [2] Measured at identical V , temperature and input voltage ...

Page 9

... NXP Semiconductors 11.3 ON resistance test circuit and waveforms Fig 8. Test circuit for measuring ON resistance ( °C. Measured at T amb Fig 9. ON resistance as a function of input voltage NX3L1G53_4 Product data sheet Low-ohmic single-pole double-throw analog switch switch GND 1 (Ω) 1.2 (1) 0 ...

Page 10

... NXP Semiconductors 1 (Ω) 1.2 0.8 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 10. ON resistance as a function of input voltage 1 1 (Ω) 0.8 0.6 0.4 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = − ...

Page 11

... NXP Semiconductors 1 (Ω) 0.8 0.6 0.4 0 125 °C. (1) T amb = 85 °C. (2) T amb = 25 °C. (3) T amb = −40 °C. (4) T amb Fig 14. ON resistance as a function of input voltage 3 12. Dynamic characteristics Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see ...

Page 12

... NXP Semiconductors Table 9. Dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); for load circuit see Symbol Parameter Conditions t break-before-make see b-m time [1] Typical values are measured at T [2] Break-before-make guaranteed by design. 12.1 Waveform and test circuits S, E input output ...

Page 13

... NXP Semiconductors a. Test circuit b. Input and output measurement points Fig 17. Test circuit for measuring break-before-make timing V Test data is given in Table Definitions test circuit Load resistance Load capacitance including jig and probe capacitance External voltage for measuring switching times. EXT V may be connected ...

Page 14

... NXP Semiconductors Table 11. Test data Supply voltage 4.3 V 12.2 Additional dynamic characteristics Table 12. Additional dynamic characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V); V ≤ specified 2.5 ns amb Symbol Parameter THD total harmonic distortion −3 dB frequency f (−3dB) response α ...

Page 15

... NXP Semiconductors 12.3 Test circuits V IL Fig 19. Test circuit for measuring total harmonic distortion V IL Adjust f voltage to obtain 0 dBm level at output. Increase f i Fig 20. Test circuit for measuring the frequency response when switch is in ON-state Adjust f voltage to obtain 0 dBm level at input. ...

Page 16

... NXP Semiconductors a. Test circuit b. Input and output pulse definitions V may be connected Fig 22. Test circuit for measuring crosstalk voltage between digital inputs and switch Fig 23. Test circuit for measuring crosstalk NX3L1G53_4 Product data sheet Low-ohmic single-pole double-throw analog switch logic input 0.5V ...

Page 17

... NXP Semiconductors a. Test circuit b. Input and output pulse definitions = ΔV × inj O L ΔV = output voltage variation generator resistance. gen V = generator voltage. gen V may be connected Fig 24. Test circuit for measuring charge injection NX3L1G53_4 Product data sheet Low-ohmic single-pole double-throw analog switch ...

Page 18

... NXP Semiconductors 13. Package outline XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1. 8× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 2.0 mm 0.5 0.04 0.17 1.9 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...

Page 19

... NXP Semiconductors XSON8U: plastic extremely thin small outline package; no leads; 8 terminals; UTLP based; body 0.5 mm terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.35 2.1 mm 0.5 0.00 0.15 1.9 OUTLINE VERSION IEC SOT996 Fig 26. Package outline SOT996-2 (XSON8U) ...

Page 20

... NXP Semiconductors XQFN8U: plastic extremely thin quad flat package; no leads; 8 terminals; UTLP based; body 1.6 x 1.6 x 0.5 mm terminal 1 index area metal area not for soldering 2 1 terminal 1 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.05 0.25 1.65 mm 0.5 0.00 ...

Page 21

... NXP Semiconductors 14. Abbreviations Table 13. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 15. Revision history Table 14. Revision history Document ID Release date NX3L1G53_4 20100127 • Modifications: Section • ...

Page 22

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 23

... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 Functional description . . . . . . . . . . . . . . . . . . . 4 9 Limiting values Recommended operating conditions Static characteristics 11.1 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 11.2 ON resistance . . . . . . . . . . . . . . . . . . . . . . . . . . 8 11 ...

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