M25PX64-VMF6TP Micron Technology Inc, M25PX64-VMF6TP Datasheet - Page 37

• Manufacturer Part Number: M25PX64-VMF6TP
• Manufacturer: Micron Technology Inc

Specifications of M25PX64-VMF6TP

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Address Bus: 24b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: SOIC W
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 8M
• Supply Current: 12mA
• Mounting: Surface Mount
• Pin Count: 16
• Lead Free Status / Rohs Status: Supplier Unconfirmed

6.7
Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the read
data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, are shifted out on serial data output (DQ1) at a
maximum frequency f
The instruction sequence is shown in
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single read data bytes at higher speed (FAST_READ) instruction.
When the highest address is reached, the address counter rolls over to 000000h, allowing
the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving Chip
Select (S) High. Chip Select (S) can be driven High at any time during data output. Any read
data bytes at higher speed (FAST_READ) instruction, while an erase, program or write
cycle is in progress, is rejected without having any effects on the cycle that is in progress.
Figure 15. Read data bytes at higher speed (FAST_READ) instruction sequence
1. Address bit A23 is don’t care.
DQ0
DQ1
S
C
DQ0
DQ1
S
C
and data-out sequence
7
0
32 33 34
1
6
High Impedance
Dummy byte
5
2
Instruction
C
, during the falling edge of Serial Clock (C).
3
4
35
3
4
36 37 38 39 40 41 42 43 44 45 46
5
2
1
6
7
0
MSB
23
7
8
Figure
22 21
9 10
6
24-bit address
DATA OUT 1
5
15.
4
3
28 29 30 31
3
2
2
(1)
1
1
0
0
47
MSB
7
6
DATA OUT 2
5
4
3
2
1
0
MSB
AI13737b
7
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