M25PX64-VMF6TP Micron Technology Inc, M25PX64-VMF6TP Datasheet - Page 51
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M25PX64-VMF6TP
Manufacturer Part Number
M25PX64-VMF6TP
Description
Manufacturer
Micron Technology Inc
Datasheet
1.M25PX64-VMF6TP.pdf
(70 pages)
Specifications of M25PX64-VMF6TP
Cell Type
NOR
Density
64Mb
Access Time (max)
8ns
Interface Type
Serial (SPI)
Address Bus
24b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
SOIC W
Sync/async
Synchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
8M
Supply Current
12mA
Mounting
Surface Mount
Pin Count
16
Lead Free Status / Rohs Status
Supplier Unconfirmed
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M25PX64-VMF6TP
Manufacturer:
NUMONYX
Quantity:
5 100
Part Number:
M25PX64-VMF6TP
Manufacturer:
ST
Quantity:
20 000
6.18
Deep power-down (DP)
Executing the deep power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the deep power-down mode). It can also be used as a software
protection mechanism, while the device is not in active use, as in this mode, the device
ignores all write, program and erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the standby power
mode (if there is no internal cycle currently in progress). But this mode is not the deep
power-down mode. The deep power-down mode can only be entered by executing the deep
power-down (DP) instruction, subsequently reducing the standby current (from I
as specified in
To take the device out of deep power-down mode, the release from deep power-down
(RDP) instruction must be issued. No other instruction must be issued while the device is in
deep power-down mode.
The deep power-down mode automatically stops at power-down, and the device always
powers up in the standby power mode.
The deep power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on serial data input (DQ0). Chip Select (S) must be driven Low for
the entire duration of the sequence.
The instruction sequence is shown in
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the deep power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t
to I
Any deep power-down (DP) instruction, while an erase, program or write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 27. Deep power-down (DP) instruction sequence
S
C
DQ0
CC2
and the deep power-down mode is entered.
Table
0
17).
1
2
Instruction
3
4
5
6
Figure
7
27.
DP
before the supply current is reduced
t
Standby mode
DP
Deep power-down mode
CC1
to I
AI13744
51/70
CC2
,