MT48LC4M32LFF5-10:G TR Micron Technology Inc, MT48LC4M32LFF5-10:G TR Datasheet - Page 25

• Manufacturer Part Number: MT48LC4M32LFF5-10:G TR
• Manufacturer: Micron Technology Inc
• Type: Mobile SDRAMr

Specifications of MT48LC4M32LFF5-10:G TR

• Organization: 4Mx32
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 22/8/7ns
• Maximum Clock Rate: 100MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 110mA
• Pin Count: 90
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Operation
BANK/ROW ACTIVATION
Figure 10:
PDF: 09005aef807f4885/Source: 09005aef8071a76b
128Mbx16x32Mobile_2.fm - Rev. L 10/07 EN
Activating a Specific Row in a Specific Bank
Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row
in that bank must be “opened.” This is accomplished via the ACTIVE command, which
selects both the bank and the row to be activated (see Figure 10).
After opening a row (issuing an ACTIVE command), a READ or WRITE command may be
issued to that row, subject to the
the clock period and rounded up to the next whole number to determine the earliest
clock edge after the ACTIVE command on which a READ or WRITE command can be
entered. For example, a
results in 2.5 clocks, rounded to 3. This is reflected in Figure 11 on page 26, which covers
any case where 2 <
specification limits from time units to clock cycles.)
A subsequent ACTIVE command to a different row in the same bank can only be issued
after the previous active row has been “closed” (precharged). The minimum time
interval between successive ACTIVE commands to the same bank is defined by
A subsequent ACTIVE command to another bank can be issued while the first bank is
being accessed, which results in a reduction of total row-access overhead. The minimum
time interval between successive ACTIVE commands to different banks is defined by
t
A0–A10, A11
RRD.
BA0, BA1
RAS#
CAS#
WE#
CKE
CLK
CS#
HIGH
t
RCD (MIN)/
t
RCD specification of 20ns with a 125 MHz clock (8ns period)
ADDRESS
ADDRESS
BANK
ROW
25
t
t
CK ≤ 3. (The same procedure is used to convert other
DON’T CARE
RCD specification.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x16, x32 Mobile SDRAM
t
RCD (MIN) should be divided by
©2001 Micron Technology, Inc. All rights reserved.
Register Definition
t
RC.