PCF8584P NXP Semiconductors, PCF8584P Datasheet - Page 6

• Manufacturer Part Number: PCF8584P
• Manufacturer: NXP Semiconductors

Specifications of PCF8584P

• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Operating Temperature (max): 85C
• Package Type: PDIP
• Rad Hardened: No
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
6
6.1
The PCF8584 acts as an interface device between
standard high-speed parallel buses and the serial I
On the I
Bidirectional data transfer between the I
parallel-bus microcontroller is carried out on a byte-wise
basis, using either an interrupt or polled handshake.
Interface to either 80XX-type (e.g. 8048, 8051, Z80) or
68000-type buses is possible. Selection of bus type is
automatically performed (see Section 6.2).
1997 Oct 21
handbook, halfpage
I
(1) Pin mnemonics between parenthesis indicate the 68000 mode
2
FUNCTIONAL DESCRIPTION
C-bus controller
SDA or SDA OUT
INT or SCL OUT
pin designations.
IACK or SDA IN
General
SCL or SCL IN
2
C-bus, it can act either as master or slave.
CLK
DB0
DB1
DB2
V SS
Fig.2 Pin configuration.
A0
10
1
2
3
4
5
6
7
8
9
PCF8584
MLA012 - 1
19
18
17
16
15
14
13
12
11
20
RESET / STROBE
WR (R/W)
CS
RD (DTACK)
DB7
DB6
DB5
DB4
DB3
V DD
2
C-bus and the
(1)
(1)
2
C-bus.
6
Table 1 Control signals utilized by the PCF8584 for
The structure of the PCF8584 is similar to that of the
I
MABXXXX/PCF84(C)XX-series of microcontrollers, but
with a modified control structure. The PCF8584 has five
internal register locations. Three of these (own address
register S0', clock register S2 and interrupt vector S3) are
used for initialization of the PCF8584. Normally they are
only written once directly after resetting of the PCF8584.
The remaining two registers function as double registers
(data buffer/shift register S0, and control/status
register S1) which are used during actual data
transmission/reception. By using these double registers,
which are separately write and read accessible, overhead
for register access is reduced. Register S0 is a
combination of a shift register and data buffer.
Register S0 performs all serial-to-parallel interfacing with
the I
Register S1 contains I
for bus access and/or monitoring.
6.2
Selection of either an 80XX mode or 68000 mode
interface is achieved by detection of the first WR-CS signal
sequence. The concept takes advantage of the fact that
the write control input is common for both types of
interfaces. An 80XX-type interface is default. If a
HIGH-to-LOW transition of WR (R/W) is detected while CS
is HIGH, the 68000-type interface mode is selected and
the DTACK output is enabled. Care must be taken that WR
and CS are stable after reset.
2
8048/
8051
68000
Z80
C-bus interface section of the Philips’
TYPE
2
C-bus.
Interface Mode Control (IMC)
microcontroller/microprocessor interfacing
R/W
yes
no
no
WR
2
yes
yes
no
C-bus status information required
yes
yes
no
R
Product specification
DTACK
PCF8584
yes
no
no
IACK
yes
yes
no