PCF8562TT NXP Semiconductors, PCF8562TT Datasheet - Page 14

• Manufacturer Part Number: PCF8562TT
• Manufacturer: NXP Semiconductors

Specifications of PCF8562TT

• Operating Supply Voltage (typ): 2.5/3.3/5V
• Number Of Digits: 16
• Number Of Segments: 128
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Pin Count: 48
• Mounting: Surface Mount
• Power Dissipation: 400mW
• Frequency (max): 400KHz
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (max): 5.5V
• Lead Free Status / Rohs Status: Compliant

NXP Semiconductors
PCF8562_2
Product data sheet
6.5.1 Internal clock
6.5.2 External clock
6.5 Oscillator
6.6 Timing
6.7 Display register
6.8 Segment outputs
6.9 Backplane outputs
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal
oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC
to pin V
Pin CLK is enabled as an external clock input by connecting pin OSC to V
The LCD frame signal frequency is determined by the clock frequency (f
A clock signal must always be supplied to the device; removing the clock may freeze the
LCD in a DC state.
The PCF8562 timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. The timing
also generates the LCD frame signal whose frequency is derived from the clock
frequency. The frame signal frequency is a fixed division integer of the clock frequency
(nominally 64 Hz) from either the internal or an external clock.
Frame frequency =
The display latch holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display latch, the
LCD segment outputs and each column of the display RAM.
The LCD drive section includes 32 segment outputs S0 to S31 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display latch. When
less than 32 segment outputs are required, the unused segment outputs should be left
open-circuit.
The LCD drive section includes four backplane outputs BP0 to BP3 which should be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode, BP3 carries the
same signal as BP1, therefore these two adjacent outputs can be tied together to give
enhanced drive capabilities. In the 1 : 2 multiplex drive mode, BP0 and BP2, BP1 and BP3
respectively carry the same signals and may also be paired to increase the drive
capabilities. In the static drive mode the same signal is carried by all four backplane
outputs and they can be connected in parallel for very high drive requirements.
SS
. After power-up, pin SDA must be HIGH to guarantee that the clock starts.
------------ -
f
CLK
24
Rev. 02 — 22 January 2007
Universal LCD driver for low multiplex rates
PCF8562
© NXP B.V. 2007. All rights reserved.
CLK
DD
).
.
14 of 36