PCF8562TT NXP Semiconductors, PCF8562TT Datasheet - Page 19

PCF8562TT

Manufacturer Part Number
PCF8562TT
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of PCF8562TT

Operating Supply Voltage (typ)
2.5/3.3/5V
Number Of Digits
16
Number Of Segments
128
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Package Type
TSSOP
Pin Count
48
Mounting
Surface Mount
Power Dissipation
400mW
Frequency (max)
400KHz
Operating Supply Voltage (min)
1.8V
Operating Supply Voltage (max)
5.5V
Lead Free Status / Rohs Status
Compliant

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NXP Semiconductors
PCF8562_2
Product data sheet
7.1 Bit transfer
7.2 Start and stop conditions
7.3 System configuration
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P), (see
A device generating a message is a ‘transmitter’, a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’, (see
Fig 11. Bit transfer
Fig 12. Definition of Start and Stop conditions
Fig 13. System configuration
SCL
SDA
SDA
SCL
TRANSMITTER/
RECEIVER
MASTER
START condition
SDA
SCL
Figure
S
Rev. 02 — 22 January 2007
12).
RECEIVER
SLAVE
data valid
data line
stable;
TRANSMITTER/
RECEIVER
Figure
Universal LCD driver for low multiplex rates
SLAVE
allowed
change
of data
Figure
11).
13).
TRANSMITTER
MASTER
STOP condition
mba607
P
PCF8562
TRANSMITTER/
© NXP B.V. 2007. All rights reserved.
RECEIVER
MASTER
mbc622
mga807
SDA
SCL
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