CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 10

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

3.0
3.1
4.0
The following subsections contain CMD (command) and DQ bus (address and data bus), database entry, arbitration logic, pipeline
and SRAM control, and full logic descriptions.
4.1
CMD[8:0] carries the CMD and its associated parameter. DQ[67:0] is used for data transfer to and from the database entries,
which comprise a data and a mask field that are organized as data and mask arrays. The DQ bus carries the Search data (of the
data and mask arrays and internal registers) during the Search command as well as the address and data during Read and/or
Write operations. The DQ bus can also carry the address information for the flow-through accesses to the external SRAMs and/or
SSRAMs.
4.2
Each database entry comprises a data and a mask field. The resultant value of the entry is “1,” “0,” or “X (don’t care),” depending
on the value in the data and mask bits. The on-chip priority encoder selects the first matching entry in the database that is nearest
to location 0.
4.3
When multiple search engines are cascaded to create large databases, the data being searched is presented to all search engines
simultaneously in the cascaded system. If multiple matches occur within the cascaded devices, arbitration logic on the search
engines will enable the winning device (with a matching entry that is closest to address 0 of the cascaded database) to drive the
SRAM bus.
Document #: 38-02041 Rev. *F
DQ[67:0]
CMD[8:0]
Logic Block Diagram
CMD Bus and DQ Bus
Database Entry (Data Array and Mask Array)
Arbitration Logic
Product Summary
Functional Description
CMDV
ACK
EOT
FULI[6:0]
PHS_L
CLK2X
RST_L
and PIO Access
ID[4:0]
Command
Decode
Full Logic
Search Successful Index Registers [7:0]
Information and Command Register
Comparand Register Pairs [15:0]
Global Mask Register Pairs [7:0]
[All registers are 68 bits wide.]
Next-Free Address Register
FULL
Burst Read Register
Burst Write Register
CMD
Configurable as
Configurable as
FULO[1:0]
Compare/PIO Data
Mask Array
Data Array
16K × 136
16K × 136
LHI[6:0]
BHI[2:0]
32K × 68
8K × 272
32K × 68
8K × 272
Arbitration
Logic
Controller
BHO[2:0]
SSF
SSV
TAP
LHO[1:0]
Pipeline
Control
SRAM
and
CYNSE70064A
TAP
OE_L
WE_L
CE_L
ALE_L
SADR[21:0]
Page 10 of 128