CYNSE70064A-66BGC Cypress Semiconductor Corp, CYNSE70064A-66BGC Datasheet - Page 17

• Manufacturer Part Number: CYNSE70064A-66BGC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYNSE70064A-66BGC

• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 1.9V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Package Type: BGA
• Mounting: Surface Mount
• Lead Free Status / Rohs Status: Not Compliant

7.8
Bit [0] of each 68-bit data entry is specially designated for use in the operation of the Learn command. For 68-bit-configured
quadrants, this bit indicates whether a location is full (bit set to 1) or empty (bit set to 0). Every Write and/or Learn command loads
the address of the first 68-bit location that contains a 0 in the entry’s bit[0]. This is stored in the NFA register (see Table 7-7). If
all the bits[0] in a device are set to 1, the CYNSE70064A asserts FULO[1:0] to 1.
For 136-bit-configured quadrants, the LSB of the NFA register is always set to 0. The host ASIC must set both bit[0] and bit[68]
in a 136-bit word to either 0 or 1 to indicate full or empty status. Both bit[0] and bit[68] must be set to either 0 or 1, (that is, the 10
or 01 settings are invalid).
Table 7-7. NFA Register
8.0
The CYNSE70064A consists of 32K × 68-bit storage cells referred to as data bits. There is a mask cell corresponding to each
data cell. Figure 8-1 shows the three organizations of the device based on the value of the CFG bits in the command register.
During a Search operation, the Search data bit (S), data array bit (D), mask array bit (M) and the global mask bit (G) are used in
the following manner to generate a match at that bit position (see Table 8-1). The entry with a match on every bit position results
in a successful Search during a Search operation.
Table 8-1. Bit Position Match
In order for a successful Search within a device to make the device the local winner in the Search operation, all 68-bit positions
must generate a match for a 68-bit entry in 68-bit configured quadrants, or all 136-bit positions must generate a match for two
consecutive even and odd 68-bit entries in quadrants configured as 136 bits, or all 272-bit positions must generate a match for
four consecutive entries aligned to four entry-page boundaries of 68-bit entries in quadrants configured as 272 bits.
An arbitration mechanism using a cascade bus determines the global winning device among the local winning devices in a Search
cycle. The global winning device drives the SRAM bus, SSV, and the SSF signals. In case of a Search failure, the device(s) with
the LDEV and LRAM bits set drives the SRAM bus, SSF, and SSV signals.
Document #: 38-02041 Rev. *F
NFA Register
NSE Architecture and Operation Overview
G
0
1
1
1
1
1
Address
32K
60
CFG = 00000000
Figure 8-1. CYNSE70064A Database WIDTH Configuration
68
M
X
0
1
1
1
1
16 K
CFG = 01010101
Data
Reserved
Masks
D
X
X
0
1
0
1
136
67–15
8 K
CFG = 10101010
Data
S
X
X
0
0
1
1
Masks
272
CYNSE70064A
Index
14–0
Match
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1
1
1
0
0
1