GS8322Z18B-200 GSI TECHNOLOGY, GS8322Z18B-200 Datasheet

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GS8322Z18B-200

Manufacturer Part Number
GS8322Z18B-200
Description
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS8322Z18B-200

Density
36Mb
Access Time (max)
7.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
133.3MHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
21b
Package Type
FBGA
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
170mA
Operating Supply Voltage (min)
2.3/3V
Operating Supply Voltage (max)
2.7/3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
119
Word Size
18b
Number Of Words
2M
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
GS8322Z18B-200
Manufacturer:
GSI
Quantity:
20 000
119, 165 & 209 BGA
Commercial Temp
Industrial Temp
Features
• NBT (No Bus Turn Around) functionality allows zero wait
• 2.5 V or 3.3 V +10%/–10% core power supply
• 2.5 V or 3.3 V I/O supply
• User-configurable Pipeline and Flow Through mode
• ZQ mode pin for user-selectable high/low output drive
• IEEE 1149.1 JTAG-compatible Boundary Scan
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2Mb, 4Mb, 8Mb, and 16Mb devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ Pin for automatic power-down
• JEDEC-standard 119-, 165- or 209-Bump BGA package
• Pb-Free packages available
Functional Description
The GS8322Z18/36/72 is a 36Mbit Synchronous Static
SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or
other pipelined read/double late write or flow through read/
single late write SRAMs, allow utilization of all available bus
bandwidth by eliminating the need to insert deselect cycles
when the device is switched from read to write cycles.
Rev: 1.07 4/2008
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Read-Write-Read bus utilization; fully pin-compatible with
both pipelined and flow through NtRAM™, NoBL™ and
ZBT™ SRAMs
Through
Pipeline
3-1-1-1
2-1-1-1
36Mb Pipelined and Flow Through
Flow
Synchronous NBT SRAM
t
KQ (x18/x36)
Curr
Curr
Curr
Curr
Curr
Curr
t
tCycle
tCycle
KQ (x72)
t
KQ
(x18)
(x36)
(x72)
(x18)
(x36)
(x72)
Parameter Synopsis
1/40
-250 -225 -200 -166 -150 -133 Unit
285
350
440
205
235
315
2.5
3.0
4.0
6.5
6.5
265
320
410
195
225
295
2.7
3.0
4.4
7.0
7.0
GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C)
Because it is a synchronous device, address, data inputs, and
read/write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable (ZZ) and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8322Z18/36/72 may be configured by the user to
operate in Pipeline or Flow Through mode. Operating as a
pipelined synchronous device, in addition to the rising-edge-
triggered registers that capture input signals, the device
incorporates a rising edge triggered output register. For read
cycles, pipelined SRAM output data is temporarily stored by
the edge-triggered output register during the access cycle and
then released to the output drivers at the next rising edge of
clock.
The GS8322Z18/36/72 is implemented with GSI's high
performance CMOS technology and is available in a JEDEC-
standard 119-bump, 165-bump or 209-bump BGA package.
245
295
370
185
210
265
3.0
3.0
5.0
7.5
7.5
220
260
320
175
200
255
3.5
3.5
6.0
8.0
8.0
210
240
300
165
190
240
3.8
3.8
6.7
8.5
8.5
185
215
265
155
175
230
4.0
4.0
7.5
8.5
8.5
mA
mA
mA
mA
mA
mA
ns
ns
ns
ns
ns
250 MHz–133 MHz 2.5
© 2002, GSI Technology
2.5 V or 3.3 V I/O
V or 3.3 V V
DD

Related parts for GS8322Z18B-200

GS8322Z18B-200 Summary of contents

Page 1

... Curr 235 225 210 200 190 (x36) Curr 315 295 265 255 240 (x72) 1/40 250 MHz–133 MHz 3.3 V I/O 4.0 ns 4.0 ns 7.5 ns 185 mA 215 mA 265 mA 8.5 ns 8.5 ns 155 mA 175 mA 230 mA © 2002, GSI Technology DD ...

Page 2

... MCH DDQ CKE DDQ MCL MCH DDQ DDQ LBO TDI Bump BGA— Body—1 mm Bump Pitch 2/ DQP DQP F B DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DDQ DQP DQP A E DDQ DDQ TDO TCK © 2002, GSI Technology ...

Page 3

... Linear Burst Order mode; active low Must Connect High Must Connect High Must Connect Low Write Enable; active low FLXDrive Output Impedance Control Low = Low Impedance [High Drive], High = High Impedance [Low Drive] Clock Enable; active low 3/40 I/Os; active low H © 2002, GSI Technology ...

Page 4

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply 4/40 © 2002, GSI Technology ...

Page 5

... V V DQD DQPD LBO TMS TDI TCK TDO 2 Body—1.27 mm Bump Pitch 5/ DDQ DQPB DQB D DQB DQB E V DQB F DDQ DQB DQB G DQB DQB DDQ DQA DQA K DQA DQA L V DQA M DDQ DQA DQA N DQPA DQA DDQ © 2002, GSI Technology ...

Page 6

... GS8322Z18B Pad Out—119-Bump BGA—Top View (Package DDQ DQB DDQ DQB V J DDQ DQB V M DDQ N DQB DDQ Bump BGA— Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) ...

Page 7

... Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply 7/ I/Os; active low C D BPR1999.05.18 © 2002, GSI Technology ...

Page 8

... GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( CKE ADV TDI A1 TDO A A TMS A0 TCK A 8/ DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2002, GSI Technology ...

Page 9

... CKE ADV TDI A1 TDO A A TMS A0 TCK A 9/ DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2002, GSI Technology ...

Page 10

... Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High Core power supply I/O and Core Ground Output driver power supply 10/ I/Os; active low C D © 2002, GSI Technology ...

Page 11

... Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( and B ) determine which bytes will be written. All or none may be activated. A write C, D 11/ and E ). Deassertion of any one of the Enable © 2002, GSI Technology ...

Page 12

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) External L Next L External L Next L External L None L Next L Next L None L None L None L None L None Current L 12/ High High High High-Z 1,2,3, High High High High High © 2002, GSI Technology Notes 1,10 2 1,2, 1,3, ...

Page 13

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow through Read/Write Control State Diagram 13/40 New Write Burst Write B D n+3 ƒ ƒ © 2002, GSI Technology ...

Page 14

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 14/40 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2002, GSI Technology ...

Page 15

... Pipeline and Flow Through Read Write Control State Diagram 15/ Data Out W (Q Valid) D Notes 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2002, GSI Technology ...

Page 16

... High Drive (Low Impedance Low Drive (High Impedance) Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 16/ Table 2: A[1:0] A[1:0] A[1:0] A[1: © 2002, GSI Technology BPR 1999.05.18 ...

Page 17

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH pipelined parts and V DD DDQ 17/40 2. The duration of SB tZZR on flow through parts. GSI NBT SS © 2002, GSI Technology ...

Page 18

... Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 (≤ 4.6 V max.) DDQ –0 +0.5 (≤ 4.6 V max.) DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2002, GSI Technology Unit Notes ...

Page 19

... V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC. DDn 19/40 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2002, GSI Technology ...

Page 20

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ V /2 DDQ Fig. 1 Output Load 1 50Ω 30pF V DDQ/2 * Distributed Test Jig Capacitance 20/40 20% tKC DD IL Typ. Max. Unit © 2002, GSI Technology ...

Page 21

... OUT I Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 21/40 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – – 2.375 V 1 3.135 V 2.4 V — © 2002, GSI Technology Max — — 0.4 V ...

Page 22

... Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) 22/40 © 2002, GSI Technology ...

Page 23

... GSI Technology -133 Unit Min Max 7.5 — ns 4.0 ns — 4.0 ns — 1.5 — ns 1.5 ns — 1.5 — ns 0.5 ns — 8.5 — ...

Page 24

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Suspend Read C Write D writeno-op tKH tKH tKC tKC tKL tKL D(A) Q(B) Q(C) 24/40 Read E Deselect E tLZ tHZ tKQ tKQX D(D) Q(E) © 2002, GSI Technology ...

Page 25

... Flow Through Mode Timing (NBT) Write B+1 Read C Cont tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 25/40 Read D Write E Read F Write tKQ tKQX tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE . The JTAG output DD © 2002, GSI Technology tKQX D(G) ...

Page 26

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( TDO should be left unconnected Description 26/40 © 2002, GSI Technology ...

Page 27

... GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 27/40 · · TDO © 2002, GSI Technology ...

Page 28

... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Not Used Configuration 28/40 GSI Technology I/O JEDEC Vendor ID Code © 2002, GSI Technology ...

Page 29

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 29/40 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2002, GSI Technology ...

Page 30

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) Description 30/40 Notes © 2002, GSI Technology ...

Page 31

... V –0.3 0 +0.3 V DD2 DD2 0 –0.3 V DD2 –300 1 uA –1 100 uA – 1.7 — V 0.4 V — – 100 mV V — DDQ 100 mV V — JTAG Port AC Test Load DQ 50Ω 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2002, GSI Technology ...

Page 32

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) JTAG Port Timing Diagram tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit 50 — ns — — ns — — ns — 32/40 tTKL tTKL © 2002, GSI Technology ...

Page 33

... Rev 1.0 Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72( ∅b e Max Units 1.70 mm 0.60 mm 0.70 mm 0. 33/ Side View Bottom View © 2002, GSI Technology ...

Page 34

... Package Dimensions—119-Bump FPBGA (Package GB (MCM), Variation 2 TOP VIEW SEATING PLANE C Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) 34/ 1.27 © 2002, GSI Technology ...

Page 35

... Package Dimensions—165-Bump FPBGA (Package E) A1 TOP SEATING C Rev: 1.07 4/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8322Z18(B/E)/GS8322Z36(B/E)/GS8322Z72(C) BOTTOM Ø0. Ø0. Ø0.40~0. 1.0 10. 15±0.0 B 0.20(4 35/ 1.0 BPR 1999.05.18 © 2002, GSI Technology ...

Page 36

... Ordering Information for GSI Synchronous Burst RAMs 1 Org Part Number GS8322Z18B-250 GS8322Z18B-225 GS8322Z18B-200 GS8322Z18B-166 GS8322Z18B-150 GS8322Z18B-133 GS8322Z18E-250 GS8322Z18E-225 GS8322Z18E-200 GS8322Z18E-166 GS8322Z18E-150 GS8322Z18E-133 GS8322Z36B-250 GS8322Z36B-225 GS8322Z36B-200 GS8322Z36B-166 GS8322Z36B-150 GS8322Z36B-133 GS8322Z36E-250 GS8322Z36E-225 GS8322Z36E-200 GS8322Z36E-166 GS8322Z36E-150 GS8322Z36E-133 512K x 72 GS8322Z72C-250 512K x 72 GS8322Z72C-225 512K x 72 ...

Page 37

... Ordering Information for GSI Synchronous Burst RAMs (Cont.) 1 Org Part Number GS8322Z18B-250I GS8322Z18B-225I GS8322Z18B-200I GS8322Z18B-166I GS8322Z18B-150I GS8322Z18B-133I GS8322Z18E-250I GS8322Z18E-225I GS8322Z18E-200I GS8322Z18E-166I GS8322Z18E-150I GS8322Z18E-133I GS8322Z36B-250I GS8322Z36B-225I GS8322Z36B-200I GS8322Z36B-166I GS8322Z36B-150I GS8322Z36B-133I GS8322Z36E-250I GS8322Z36E-225I GS8322Z36E-200I GS8322Z36E-166I GS8322Z36E-150I GS8322Z36E-133I 512K x 72 GS8322Z72C-250I 512K x 72 GS8322Z72C-225I ...

Page 38

... GS8322Z18GB-225I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 39

... GS8322Z72GC-133I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8322Z18B-150IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 40

... Added variation information to package mechanicals • Pb-free information added Content • Corrected AC Electrical Characteristics Table Content • Rev1.06a: updated coplanarity for 119, 165 BGA mechanical, removed Status column from Ordering Information table. • Updated Synchronous Truth Table (pg. 12) Content 40/40 © 2002, GSI Technology ...

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