GC80960RD66 Intel, GC80960RD66 Datasheet - Page 10

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Intel
Functional Overview
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
10
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i960
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RX I/O Processor at 3.3 Volts
Key Functional Units
The PCI-to-PCI bridge unit (referred to as “bridge”) connects two independent PCI buses.
It is fully compliant with the PCI-to-PCI Bridge Architecture Specification, Revision 1.0
published by the PCI Special Interest Group. It allows certain bus transactions on one PCI
bus to be forwarded to the other PCI bus. Dedicated data queues support high
performance bandwidth on the PCI buses. The Product Name supports PCI 64-bit Dual
Address Cycle (DAC) addressing.
The bridge has dedicated PCI configuration space that is accessible through the primary
PCI bus.
Private PCI Device Support
A key design feature is that the 80960RX explicitly supports private PCI devices on the
secondary PCI bus without being detected by PCI configuration software. The bridge and
Address Translation Unit work together to hide private devices from PCI configuration
cycles and allow these devices to use a private PCI address space. The Address
Translation Unit uses normal PCI configuration cycles to configure these devices.
DMA Controller
The DMA Controller supports low-latency, high-throughput data transfers between PCI
bus agents and 80960 local memory. Three separate DMA channels accommodate data
transfers: two for primary PCI bus, one for the secondary PCI bus. The DMA Controller
supports chaining and unaligned data transfers. It is programmable only through the Intel
i960
Address Translation Unit
The Address Translation Unit (ATU) allows PCI transactions direct access to the 80960RX
local memory. The 80960RX has direct access to both PCI buses. The ATU supports
transactions between PCI address space and 80960RX address space.
Address translation is controlled through programmable registers accessible from both the
PCI interface and the 80960 core. Dual access to registers allows flexibility in mapping the
two address spaces.
Messaging Unit
The Messaging Unit (MU) provides data transfer between the PCI system and the
80960RX. It uses interrupts to notify each system when new data arrives. The MU has
four messaging mechanisms. Each allows a host processor or external PCI device and
the 80960RX to communicate through message passing and interrupt generation. The
four mechanisms are Message Registers, Doorbell Registers, Circular Queues, and Index
Registers.
PCI-to-PCI Bridge Unit
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core processor.
Datasheet
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