GC80960RD66 Intel, GC80960RD66 Datasheet - Page 27

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Table 8.
Datasheet
Memory Controller Signal Descriptions (Sheet 1 of 2)
LEAF1:0#
DWE1:0#
CAS7:0#
DALE1:0
CE1:0#
Name
DP3:0
Type
H(Q)
P(Q)
H(Q)
P(Q)
H(Q)
P(Q)
R(X)
H(Q)
P(Q)
H(Q)
P(Q)
H(Q)
P(Q)
R(1)
R(1)
R(0)
R(1)
R(1)
I/O
O
O
O
O
O
COLUMN ADDRESS STROBE signals are used for DRAM accesses and are
asserted when the MA11:0 signals contain a valid column address. CAS7:0#
signals are asserted during refresh.
Non-Interleaved Operation:
Interleaved Operation:
CHIP ENABLE signals indicate an access to one of the two SRAM/ FLASH/
ROM memory banks. CE0# and CE1# are never asserted at the same time.
These signals are valid during the entire memory operation. CE0# is asserted
for accesses to memory bank 0. CE1# is asserted for accesses to memory
bank 1.
DRAM ADDRESS LATCH ENABLE signals support external address
demultiplexing of the MA11:0 address lines for interleaved DRAM systems.
Use these to directly interface to ‘373’ type latches. These signals are only
valid for accesses to interleaved memory systems. DALE0 is asserted during a
valid even leaf address. DALE1 is asserted during a valid odd leaf address.
DATA PARITY carries the parity information for DRAM accesses. Each parity
bit corresponds to a group of 8 data bus signals as follows:
The memory controller generates parity information for local bus writes during
data cycles. During read data cycles, the memory controller checks parity and
provides notification of parity errors on the clock following the data cycle.
Parity checking and polarity are user-programmable. Parity generation and
checking are valid only for data lines that have their associated enable bits
asserted.
DRAM WRITE ENABLE signals distinguish between read and write accesses
to DRAM. DWE1:0# lines are asserted for writes and deasserted for reads.
CAS7:0# determine valid bytes lanes during the access. These two outputs are
functionally equivalent for all DRAM accesses; these provide increased drive
capability for heavily loaded systems.
LEAF ENABLE signals control the data output enables of the memory system
during an interleaved DRAM read access. Use these to directly interface to
either DRAM or transceiver output enable signals. LEAF0# is asserted during
an even leaf access. LEAF1# is asserted during an odd leaf access.
DP0 — AD7:0DP2 — AD23:16
DP1 — AD15:8DP3 — AD31:24
CAS0#
CAS1#
CAS2#
CAS3#
CAS0# = BE0#
CAS1# = BE1#
CAS2# = BE2#
CAS3# = BE3#
CAS4# = BE0#
CAS5# = BE1#
CAS6# = BE2#
CAS7# = BE3#
,
,
,
,
CAS4#
CAS5#
CAS6#
CAS7#
=
=
=
=
Even leaf lane access
Even leaf lane access
Even leaf lane access
Even leaf lane access
Odd leaf lane access
Odd leaf lane access
Odd leaf lane access
Odd leaf lane access
BE0#
BE1#
BE2#
BE3#
Intel
®
Description
i960
lane access
lane access
lane access
lane access
®
RX I/O Processor at 3.3 Volts
Package Information
27