GC80960RD66 Intel, GC80960RD66 Datasheet - Page 12

• Manufacturer Part Number: GC80960RD66
• Manufacturer: Intel

Specifications of GC80960RD66

• Family Name: i960 RX
• Device Core: 80960
• Device Core Size: 32b
• Frequency (max): 66MHz
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: HLBGA
• Lead Free Status / Rohs Status: Not Compliant

Intel
Functional Overview
2.2
Figure 2.
12
®
i960
®
RX I/O Processor at 3.3 Volts
Intel
The processing power of the 80960RX comes from the 80960JF processor core. The
80960JF is a new, scalar implementation of the 80960 Core Architecture.
a block diagram of the 80960JF Core processor.
Factors that contribute to the 80960 family core performance include:
The 80960 core operates out of its own 32-bit address space, which is independent of the
PCI address space. The local bus memory can be:
80960JF Core Block Diagram
•
•
•
•
•
•
•
•
•
•
•
S_CLK
SRC1
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
4 Kbyte two-way set-associative, integrated instruction cache
2 Kbyte direct-mapped, integrated data cache
1 Kbyte integrated data RAM delivers zero wait state program data
Made visible to the PCI address space
Kept private to the 80960 core
Allocated as a combination of the two
TAP
Local Register
5
Global / Local
Register File
®
Cache
i960
8-Set
SRC2 DST
Boundary Scan
PLL, Clocks,
Power Mgmt
3 Independent 32-Bit SRC1, SRC2, and DST Buses
128
Controller
®
Core Features (Intel
Multiply
Divide
Unit
4 Kbyte Two-Way Set
Instruction Sequencer
Generation
Execution
Instruction Cache
Effective
Address
Address
Constants
and
Unit
Associative
Control
®
32-bit Data
32-bit Addr
Interface
Memory
80960JF)
Unit
address / data
32-bit buses
Interrupt Controller
Register Interface
Physical Region
Memory-Mapped
Programmable
Bus Request
Mapped Data
Configuration
Two 32-Bit
Control Unit
Data RAM
1 Kbyte
Queues
2 Kbyte
Cache
Timers
Direct
Bus
Figure 2
Datasheet
Data Bus
Control
Address/
Interrupt
Port
shows
32
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