JS28F640J3D75 Micron Technology Inc, JS28F640J3D75 Datasheet - Page 30
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
JS28F640J3D75
Manufacturer Part Number
JS28F640J3D75
Description
Manufacturer
Micron Technology Inc
Datasheet
1.JS28F640J3D75.pdf
(68 pages)
Specifications of JS28F640J3D75
Cell Type
NOR
Density
64Mb
Access Time (max)
75ns
Interface Type
Parallel
Boot Type
Not Required
Address Bus
23/22Bit
Operating Supply Voltage (typ)
3/3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Program/erase Volt (typ)
2.7 to 3.6V
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
8M/4M
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
JS28F640J3D75
Manufacturer:
INTEL
Quantity:
5 530
Company:
Part Number:
JS28F640J3D75
Manufacturer:
INTEL
Quantity:
9
Part Number:
JS28F640J3D75
Manufacturer:
INTEL
Quantity:
20 000
Company:
Part Number:
JS28F640J3D75A
Manufacturer:
INTEL
Quantity:
5 530
Company:
Part Number:
JS28F640J3D75A
Manufacturer:
INTEL
Quantity:
5 530
Company:
Part Number:
JS28F640J3D75A
Manufacturer:
NUMONYX
Quantity:
3 456
Part Number:
JS28F640J3D75A
Manufacturer:
NUMONYX
Quantity:
20 000
Part Number:
JS28F640J3D75E
Manufacturer:
MUMONYS
Quantity:
20 000
Part Number:
JS28F640J3D75ES
Manufacturer:
INTEL
Quantity:
20 000
Table 13: Reset Specifications
7.5
Figure 17: AC Input/Output Reference Waveform
Note:
Figure 18: Transient Equivalent Testing Load Circuit
Note:
Figure 19: Test Configuration
Datasheet
30
Notes:
1.
2.
3.
P1
P2
P3
#
AC test inputs are driven at V
V
C
These specifications are valid for all product versions (packages and speeds).
If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing then the
minimum required RP# Pulse Low Time is 100 ns.
A reset time, t
valid.
CCQ
L
Symbol
t
Includes Jig Capacitance
t
t
VCCPH
PHRH
PLPH
/2 V (50% of V
AC Test Conditions
V
RP# Pulse Low Time
(If RP# is tied to V
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
Vcc Power Valid to RP# de-assertion (high)
CCQ
0.0
Test Configuration
PHQV
V
Input V
CCQ
, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are
CCQ
= V
). Input rise and fall times (10% to 90%) < 5 ns.
CCQMIN
CCQ
CCQ
/2
CC
for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
, this specification is not applicable)
Under Test
Device
Parameter
Test Points
Numonyx™ Embedded Flash Memory (J3 v. D)
C
L
Out
Min
25
60
C
L
V
30
CCQ
(pF)
Max
100
/2
Output
Unit
µs
ns
µs
November 2007
308551-05
Notes
1,2
1,3