MD3331-D64-V3-X SanDisk, MD3331-D64-V3-X Datasheet - Page 19

• Manufacturer Part Number: MD3331-D64-V3-X
• Manufacturer: SanDisk
• Type: Flash Diskr

Specifications of MD3331-D64-V3-X

• Density: 64MByte
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: FBGA
• Mounting: Surface Mount
• Pin Count: 69
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 3.6V
• Programmable: Yes
• Lead Free Status / Rohs Status: Not Compliant

3.2
The system interface block provides an easy-to-integrate SRAM-like (also EEPROM-like) interface
to Mobile DiskOnChip Plus, enabling it to interface with various CPU interfaces, such as a local
bus, ISA bus, SRAM interface, EEPROM interface or any other compatible interface. In addition,
the EEPROM-like interface enables direct access to the Programmable Boot Block to permit XIP
functionality during system initialization.
A 13-bit wide address bus enables access to the DiskOnChip 8KB memory window (as shown in
Section 6.2). The 16-bit data bus permits 16-bit wide access to the host. The internal access to the
flash is 8-bit.
The Chip Enable (CE#), Write Enable (WE#) and Output Enable (OE#) signals trigger read and
write cycles. A write cycle occurs while both the CE# and the WE# inputs are asserted. Similarly, a
read cycle occurs while both the CE# and OE# inputs are asserted. Note that Mobile DiskOnChip
Plus does not require a clock signal. Mobile DiskOnChip Plus features a unique analog static
design, optimized for minimal power consumption. The CE#, WE# and OE# signals trigger the
controller (e.g., system interface block, bus control and data pipeline) and flash access.
The Reset In (RSTIN#) and Busy (BUSY#) control signals are used in the reset phase. See
Section 5.2 for further details.
The Interrupt Request (IRQ#) signal can be used when long I/O operations, such as Block Erase,
delay the CPU resources. The signal is also asserted when a Data Protection violation has occurred.
When this signal is implemented, the CPU can run other tasks and only returns to continue
read/write operations with Mobile DiskOnChip Plus after the IRQ# signal has been asserted and an
Interrupt Handling Routine (implemented in the OS) has been called to return control to the
TrueFFS driver.
3.3
The Configuration Interface block enables the designer to configure Mobile DiskOnChip Plus to
operate in different modes. The identification signals (ID[1:0]) are used for identifying the relevant
DiskOnChip device in a cascaded configuration (see Section 9.6 on cascading for further details).
The Lock (LOCK#) signal enables hard-wire hardware-controlled protection of code and data, as
described below. For a standard interface, the Interface Configuration (IF_CFG) signal configures
Mobile DiskOnChip Plus for 16-bit or 8-bit data access (see Section 9.5.4).
3.4
The protection and security-enabling block, consisting of read/write protection, UID and OTP area,
enables advanced data and code security and protection. Located on the main route of traffic
between the host and the flash, this block monitors and controls all data and code transactions to
and from Mobile DiskOnChip Plus.
3.4.1
Data and code protection is implemented through a Protection State Machine (PSM). The user can
configure one or two independently programmable areas of the flash memory as read protected, write
protected, or read/write protected.
19
System Interface
Configuration Interface
Protection and Security-Enabling Features
Read/Write Protection
Data Sheet, Rev. 1.8
Mobile DiskOnChip Plus 16/32MByte
95-SR-000-10-8L