TC58DVM72A1FT00 Toshiba, TC58DVM72A1FT00 Datasheet
TC58DVM72A1FT00
Specifications of TC58DVM72A1FT00
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TC58DVM72A1FT00 Summary of contents
Page 1
... NC 5 GND CLE 16 ALE PROM PINNAMES NC I/ I/ CLE ALE I/O4 32 GND I/ TC58DVM72A1FT00 I/O port Chip enable Write enable Read enable Command latch enable Address latch enable Write protect Ready/Busy Ground input Power supply Ground 2003-03-19 1/34 ...
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... This parameter is periodically sampled and is not tested for every device. Status register Address register Command register Control HV generator − 0.6 V~V CC PARAMETER CONDITION V V TC58DVM72A1FT00 V CC Column buffer Column decoder Data register Sense amp Memory cell array VALUE − 0.6~4.6 − 0.6~4 ≦ 4.6 V) ...
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... OUT = cycle = cycle = cycle V/V IH − − pin V OL TC58DVM72A1FT00 MIN TYP. MAX 1004 1024 MIN TYP. MAX 2.7 3.3 3.6 + 0.3 2 − 0.3 * 0.8 MIN TYP. 10 cycle ...
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... CE High to Ready(When interrupted Read Mode) CRY t Device Reset Time (Read/Program/Erase) RST AC TEST CONDITIONS PARAMETER Input level Input pulse rise and fall time Input comparison level Output data comparison level Output load PARAMETER TC58DVM72A1FT00 MIN MAX UNIT ...
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... BERASE (1): Refer to Application Note (12) toward the end of this document. is greater than or equal to 100 ns. If the delay CEH signal stays Ready. t CEH 526 527 A MIN TC58DVM72A1FT00 pin. ≥ 100 → Busy signal is not output. A Busy TYP. MAX UNIT µ s ...
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... TIMING DIAGRAMS Latch Timing Diagram for Command/Address/Data CLE ALE I/O1 to I/O8 Command Input Cycle Timing Diagram CLE t CLS ALS ALE I/O1 to I/O8 Setup Time CLH ALH TC58DVM72A1FT00 Hold Time 2003-03-19 6/34 ...
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... Address Input Cycle Timing Diagram t CLS CLE ALS ALE I/O1 t I/O8 o Data Input Cycle Timing Diagram CLE ALS ALE WE I/ A16 TC58DVM72A1FT00 ALH A17 to A23 : CLH 527 2003-03-19 7/34 ...
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... Serial Read Cycle Timing Diagram REA I/ Status Read Cycle Timing Diagram CLE t CLS I/ I/ 70H represents the hexadecimal number REH RHZ REA RHZ t CLS t CLH WHC t WHR 70H * TC58DVM72A1FT00 CHZ REA RHZ t CEA t t CSTO CHZ RSTO RHZ Status output : 2003-03-19 8/34 IL ...
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... CLS CLH ALH ALS ALE I/O1 00H I/O8 Column address Read Operation using 00H Command 255 ALH A16 A17toA23 ALH A16 A17toA23 N * TC58DVM72A1FT00 t AR2 REA OUT OUT OUT CHZ t AR2 REA RHZ OUT OUT OUT 2003-03-19 9/34 D OUT 527 IL IL ...
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... DS DH I/O1 50H to I/ Read Operation using 50H Command N: 0 to15 t t ALS ALH A16 A17toA23 Column address ALS ALH A16 A17toA23 Column address N * TC58DVM72A1FT00 t AR2 REA D D OUT OUT 256 + M 256 + AR2 REA D D OUT OUT 512 + M 512 + 2003-03-19 10/34 ...
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... Column address Sequential Read (2) Timing Diagram CLE CE WE ALE RE I/O1 01H A16 A17toA23 to I/O8 Column address A17toA23 N Page t R address M Page M access Page t 256 + 256 + R address Page M access TC58DVM72A1FT00 527 527 t R Page access : 527 527 t R Page access : 2003-03-19 11/34 ...
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... Sequential Read (3) Timing Diagram CLE CE WE ALE RE I/O1 50H A16 A17toA23 to I/O8 Column address Page t 512 + 512 + R address Page M access TC58DVM72A1FT00 527 512 513 t 512 + Page access : 2003-03-19 12/34 527 ...
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... Setup command t ALH t ALS A16 A17toA23 not input data while data is being output ALH WB D0H Erase Start command : not input data while data is being output TC58DVM72A1FT00 t PROG 10H 70H 527 t BERASE Status 70H output Status Read Busy command 2003-03-19 13/ Status output ...
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... ID Read Operation Timing Diagram CLE t CLS t CLS ALH ALS ALE I/O1 90H to I/ CEA t ALH t ALEA t REAID 00 Address Maker code input TC58DVM72A1FT00 t REAID 98H 73H Device code : 2003-03-19 14/34 ...
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... BY The output signal is used to indicate the operating condition of the device. The = L) during the Program, Erase and Read operations and will return to Ready state Busy state ( after completion of the operation. The output buffer for this signal is an open drain. TC58DVM72A1FT00 GND ...
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... Capacity = 528 bytes × 32 pages × 1024 blocks 8I/O I/O6 I/O5 I/O4 I/O3 I/ A14 A13 A12 A11 A10 A22 A21 A20 A19 A18 TC58DVM72A1FT00 I/O1 A0~A7: Column address A9~A23: Page address A0 A14~A23: Block address A9 A9~A13: NAND address in block A17 2003-03-19 16/34 ...
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... Output Deselect L Standby CLE ALE Second Cycle Acceptable while Busy 80 00 01 50 70 90 ALE TC58DVM72A1FT00 HEX data bit assignment (Example) Serial data input: 80H I/ I/O1~I/O8 L Data output H High impedance * High impedance 2003-03-19 17/ V/Vcc I/O1 Power Active ...
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... The operation of the device after input of the 01H command is the same as that of Read mode (1). If the start pointer set after column address 256, use Read mode (2). Cell array TC58DVM72A1FT00 WE in the third cycle (after the CE signal must stay 2003-03-19 18/34 ...
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... A4-to-A7 address. (An 00H command is necessary to move the pointer back to the 0-to-511 main memory cell location.) Data output t R Busy m (01H) n/2 A Sequential Read (2) TC58DVM72A1FT00 Data output Busy Busy (50H Sequential Read (3) ...
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... Device 2 3 Busy 70H Status on Device 1 Figure 6. Status Read timing application example pin signals from multiple devices are wired together as shown in the TC58DVM72A1FT00 The Pass/Fail status on I/O1 is only valid when the device is in the Ready state Device Device N Status on Device N 2003-03-19 20/34 ...
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... After programming, the programmed data is transferred back to the register to be automatically verified by the device. If the programming does not succeed, the Program/Verify operation is repeated by the device until success is achieved or until the maximum loop number set in the device is reached. D0 Erase Start command Busy TC58DVM72A1FT00 Pass 70 I/O Status Read Fail command RY / ...
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... The second FF (max 10 µ RST FF FF (max 6 µ RST command is invalid, but the third TC58DVM72A1FT00 00 (max 500 µ RST I/O status: Pass/Fail → Pass Ready/Busy → Ready I/O status: Ready/Busy → Busy ( command is valid. 2003-03-19 22/34 Figure 8. Figure 9. 00 Figure 10. ...
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... Table 6. ID Codes read out by ID read command 90H I/O8 Maker code 1 Device code 0 t CEA t ALEA t REAID 00 Address Maker code and t refer to the AC Characteristics. REAID CEA ALEA Figure 13. ID Read timing I/O7 I/O6 I/O5 I/ TC58DVM72A1FT00 98H 73H Device code I/O3 I/O2 I/ 2003-03-19 23/34 Hex Data 98H 73H ...
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... Operation Figure 15. Power-on/off Sequence becomes 2 recommends starting access after about CC FF Reset Figure 16. 10 For this operation the “FFH” command is needed. Programming cannot be executed. TC58DVM72A1FT00 reaches 2.5 V and CE signal is kept high in Don’t care V IL 2003-03-19 24/34 ...
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... Read mode. In this case, data output starts automatically from address N and address input is unnecessary Ex.) Random page program (Prohibition) DATA IN: Data (1) (1) Page 0 (2) Page 1 Page 2 (3) (16) Page 15 (32) Page 31 Figure 17. page programming within a block Status Read command input Figure 18. TC58DVM72A1FT00 Data (32) Data register (2) (16) (3) (1) (32) 00 [A] 70 Status Read Status output 2003-03-19 25/34 ...
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... C area C area Start point Add Start point B area A area Add DIN Start point C Area Add Start point B Area Figure 20. Example of How to Set the Pointer TC58DVM72A1FT00 n/2-1 n/2 n Pointer control Figure 19 Pointer control 50H Add Start point C area 00H Add Start point ...
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... This data may vary from device to device. We recommend that you use this data as a reference when selecting a resistor value DIN Ready 1.5 µ s 1.0 µ 0.5 µ Ω TC58DVM72A1FT00 buffer consists of an open drain Busy 25° Ω Ω Ω R 2003-03-19 27/ ...
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... The Erase and Program operations are automatically reset when WP goes Low. The operations are enabled and disabled as follows: Enable Programming WE DIN (100 ns min) WW Disable Programming WE DIN (100 ns min) WW Enable Erasing WE DIN (100 ns min) WW Disable Erasing WE DIN (100 ns min TC58DVM72A1FT00 2003-03-19 28/34 ...
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... Although the device may read in a fourth address ignored inside the chip. Read operation CLE CE WE ALE I/O 00H, 01H, 50H Internal read operation starts when Program operation CLE CE WE ALE I/O 80H Address input WE goes High in the third cycle. Figure 22. Address input Ignored Figure 23. TC58DVM72A1FT00 Ignored Data input 2003-03-19 29/34 ...
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... Busy state. (Refer to Figure 25.) I/O 00H/01H/50H Hence the RE clock input must start after the address input. All 1s Data Pattern 2 All 1s Data Pattern 2 Figure 24. Figure 25. TC58DVM72A1FT00 All 1s All 1s Data Pattern 3 Data Pattern 3 Address input 2003-03-19 30/34 ...
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... Valid (Good) Block Number 1004 Start Block Fail Read Check Pass Block No. = 1024 Yes End Figure 27 TC58DVM72A1FT00 TYP. MAX 1024 Read Check : to verify the column address 517 bytes of the first page in the block with FFh Bad Block * 1 2003-03-19 31/34 UNIT ...
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... Block Verify after Program → Retry (2) ECC When an error happens in Block A, try to reprogram the data into another Block (Block B) by loading from an external buffer. Then, Block A prevent further system accesses to Block A (by creating a bad block table or by using an another appropriate scheme). Block B Figure 28. TC58DVM72A1FT00 2003-03-19 32/34 ...
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... Package Dimensions Weight: 0.53g (typ.) TC58DVM72A1FT00 Unit : mm 2003-03-19 33/34 ...
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... The products described in this document are subject to the foreign exchange and foreign trade laws. • TOSHIBA products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. TC58DVM72A1FT00 030619EBA 2003-03-19 34/34 ...