TC58DVM72A1FT00 Toshiba, TC58DVM72A1FT00 Datasheet - Page 16

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TC58DVM72A1FT00

Manufacturer Part Number
TC58DVM72A1FT00
Description
Manufacturer
Toshiba
Datasheet

Specifications of TC58DVM72A1FT00

Cell Type
NAND
Density
128Mb
Access Time (max)
35ns
Interface Type
Parallel
Address Bus
8b
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8b
Number Of Words
16M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

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Schematic Cell Layout and Address Assignment
An address is read in via the I/O port over three consecutive clock cycles, as shown in Table 1.
32768 pages
1024 blocks
Table 1. Addressing
First cycle
Second cycle
Third cycle
* : A8 is automatically set to Low or High by a 00H command or a 01H command.
*
The Program operation works on page units while the Erase operation works on block units.
I/O8 must be set to Low in the third cycle.
Figure 2. Schematic Cell Layout
512
528
I/O8
A16
A7
*L
16
I/O7
A15
A23
A6
I/O6
A14
A22
A5
8I/O
I/O8
32 pages
1 block
I/O5
A13
A21
A4
I/O1
I/O4
A12
A20
A3
for main memory storage and 16 bytes are for redundancy
or for other uses.
I/O3
A11
A19
A2
A page consists of 528 bytes in which 512 bytes are used
1 page = 528 bytes
1 block = 528 bytes × 32 pages = (16K + 512) bytes
Capacity = 528 bytes × 32 pages × 1024 blocks
I/O2
A10
A18
A1
I/O1
A17
A9
A0
A0~A7:
A9~A23: Page address
A14~A23: Block address
A9~A13: NAND address in block
TC58DVM72A1FT00
Column address
2003-03-19 16/34

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