ELANSC410-33AC AMD (ADVANCED MICRO DEVICES), ELANSC410-33AC Datasheet - Page 19

• Manufacturer Part Number: ELANSC410-33AC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of ELANSC410-33AC

• Lead Free Status / Rohs Status: Not Compliant

The ÉlanSC400 and ÉlanSC410 microcontrollers sup-
port the data bus configurations listed below. External
transceivers or buffers can be used to isolate the
buses.
See Figure 2 on page 22 and Figure 3 on page 23 for
block diagrams of example systems.
The ÉlanSC400 and ÉlanSC410 microcontrollers offer
flexibility in configuring the ROM and DRAM data
buses for different widths. The widths (8/16/32 bits) for
ROMCS0 are programmed during power-up through
two pinstraps, CFG0 and CFG1. The DRAM widths
(16/32 bits) are programmed through configuration
registers. Up to four 16- or 32-bit banks of DRAM are
supported.
Two of the three ROM/Flash memory chip selects
(ROMCS2–ROMCS0) can be remapped to a PC Card
socket via pinstrap or software control. This feature
supports reprogramming of soldered-down Flash
memory boot devices and also simplifies testing of
BIOS/XIP (execute in place) OS code.
Address Buses
There are two external address buses on the
ÉlanSC400 and ÉlanSC410 microcontrollers.
The SA bus is shared between the ISA bus, the
VL-bus, the ROM/Flash memory controller and, on the
ÉlanSC400 microcontroller, the PC Card controller.
The ÉlanSC400 and ÉlanSC410 microcontrollers
provide programmable drive strengths in the I/O
buffers to accommodate loading for various system
configurations.
16-bit DRAM bus, 8-/16-bit ROM, 32-bit VL-bus
disabled, internal graphics controller enabled/
disabled
16-/32-bit DRAM bus, 8/16-bit ROM, 32-bit VL-bus
enabled/disabled, internal graphics controller
disabled
16-/32-bit DRAM bus, 32-bit ROM, 32-bit VL-bus
enabled/disabled, internal graphics controller
disabled
System Address Bus: The SA25–SA0 system ad-
dress bus outputs the physical memory or I/O port
latched addresses. These addresses are used by
all external peripheral devices other than main sys-
tem DRAM. In addition, the system address bus is
the local address bus in VL-bus mode.
DRAM Address Bus: DRAM row and column ad-
dresses are multiplexed onto the DRAM address
bus (MA12–MA0). Row addresses are driven onto
this bus and are valid upon the falling edge of RAS.
Column addresses are driven onto this bus and are
valid upon the falling edge of CAS.
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
Memory Management
The ÉlanSC400 and ÉlanSC410 microcontrollers man-
age up to nine separate physical device memory ad-
dress spaces. All but the ISA memory address space
can have a depth of up to 64 Mbyte each. The ISA bus
memory area is limited to 16 Mbyte, as defined by ISA
specifications. The microcontroller will drive all 26 ad-
dress lines on ISA cycles to allow up to 64-Mbyte ad-
dress space, as described in the memory management
section of the ÉlanSC400 and ÉlanSC410 Microcon-
trollers User’s Manual (order #21030)—refer to the
subsection on ISA bus addressing). The nine memory
spaces are:
The system memory address space (DRAM) is acces-
sible using direct-mapped CPU addresses and can
also be accessed by the CPU in an indirect method
using the Memory Mapping System (MMS). On the
ÉlanSC400 microcontroller, DRAM is also accessible
by the integrated graphics controller if enabled.
The ROM0 address space is partially accessible via a
direct mapping of the CPU address bus and partially
accessible via the MMS. The ROM1 and ROM2
address spaces are only accessible indirectly using the
MMS.
On the ÉlanSC400 microcontroller, the PC Card ad-
dress spaces are accessed through a separate,
82365SL-compatible address mapping system.
The ISA/VL-bus address space is accessible as a
direct mapping of the CPU address bus. ISA memory
cycles are generated when the CPU generates a
memory cycle that is not detected as an access to any
other memory space. An ISA bus memory cycle can
also be generated if the CPU generates a memory
address that resides in the ISA overlapping memory
region window. This window can be defined to overlay
any system memory region below 16 Mbyte.
System memory address space (DRAM)
ROM0 memory address space (ROMCS0 signal)
ROM1 memory address space (ROMCS1 signal)
ROM2 memory address space (ROMCS2 signal)
PC Card Socket A memory address spaces (com-
mon and attribute) (ÉlanSC400 microcontroller only)
PC Card Socket B memory address spaces (com-
mon and attribute) (ÉlanSC400 microcontroller only)
External ISA/VL-bus memory address space
19