ISP1362BD NXP Semiconductors, ISP1362BD Datasheet - Page 90

• Manufacturer Part Number: ISP1362BD
• Description: USB Interface IC USB OTG CONTROLLER
• Manufacturer: NXP Semiconductors

Specifications of ISP1362BD

• Operating Supply Voltage: 3 V to 3.6 V
• Lead Free Status / Rohs Status: Details
• Other names: ISP1362BD,157

NXP Semiconductors
ISP1362_5
Product data sheet
Table 64.
Bit
15
14
13
12
11
10
9
8
7
6
Symbol
DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the
GlobalPowerDown
ConnectPullDown_DS2
ConnectPullDown_DS1
SuspendClkNotStop
AnalogOCEnable
OneINT
DACKMode
OneDMA
DACKInputPolarity
HcHardwareConfiguration register: bit description
Rev. 05 — 8 May 2007
Description
D_SUSPEND/D_WAKEUP and H_SUSPEND/H_WAKEUP
pins. Therefore, these pins will always remain HIGH and
pulling them LOW does not wake-up the Host Controller and
the Peripheral Controller.
Set this bit to logic 1 to reduce power consumption of the
OTG ATX in suspend mode.
0 — disconnect built-in pull-down resistors on H_DM2 and
H_DP2
1 — connect built-in pull-down resistors on H_DM2 and
H_DP2 for the downstream port 2
Remark: Port 2 is always used as a host port.
0 — disconnect built-in pull-down resistors on OTG_DM1 and
OTG_DP1
1 — connect built-in pull-down resistors on OTG_DM1 and
OTG_DP1
Remark: This bit is effective only when port 1 is configured as
the host port (the OTGMODE pin is HIGH, and the ID pin is
LOW). When port 1 is configured as the OTG port, (the
OTGMODE pin is LOW), the pull-down resistors on
OTG_DM1 and OTG_DP1 are controlled by the
LOC_PULL_DN_DP and LOC_PULL_DN_DM bits of the
OtgControl register.
0 — clock can be stopped when suspended
1 — clock cannot be stopped when suspended
0 — use external overcurrent detection; digital input
1 — use on-chip overcurrent detection; analog input
0 — Host Controller interrupt routed to INT1, Peripheral
Controller interrupt routed to INT2
1 — Host Controller and Peripheral Controller interrupts
routed to INT1 only, INT2 is unused
0 — normal operation; DACK1 is used with read and write
signals
1 — reserved
0 — Host Controller DMA request and acknowledge are
routed to DREQ1 and DACK1, Peripheral Controller DMA
request and acknowledge are routed to DREQ2 and DACK2
1 — Host Controller and Peripheral Controller DMA requests
and acknowledges are routed to DREQ1 and DACK1;
DREQ2 and DACK2 unused
0 — DACK1 is active LOW
1 — DACK1 is active HIGH
Single-chip USB OTG Controller
© NXP B.V. 2007. All rights reserved.
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