IS63LV1024-15K INTEGRATED SILICON SOLUTION (ISSI), IS63LV1024-15K Datasheet - Page 8

• Manufacturer Part Number: IS63LV1024-15K
• Description: SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 15ns 32-Pin SOJ
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)

Specifications of IS63LV1024-15K

• Package: 32SOJ
• Timing Type: Asynchronous
• Density: 1 Mb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 8 Bit
• Number Of Ports: 1
• Number Of Words: 128K

AC WAVEFORMS
WRITE CYCLE NO. 2
IS63LV1024
IS63LV1024L
8
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
2. I/O will assume the High-Z state if OE > V
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
ADDRESS
ADDRESS
D
D
OUT
OUT
WE
WE
D
D
OE
OE
CE
CE
IN
IN
LOW
LOW
LOW
t
SA
(1)
t
DATA UNDEFINED
DATA UNDEFINED
(WE Controlled: OE is LOW During Write Cycle)
SA
(WE Controlled,
IH
.
Integrated Silicon Solution, Inc. — www.issi.com —
= HIGH during Write Cycle)
VALID ADDRESS
t
t
t
t
AW
AW
HZWE
HZWE
VALID ADDRESS
t
t
PWE1
WC
t
t
PWE2
WC
HIGH-Z
HIGH-Z
t
t
SD
SD
DATA
DATA
IN
IN
VALID
VALID
t
t
HD
HD
t
t
LZWE
LZWE
t
t
HA
HA
1-800-379-4774
CE_WR2.eps
CE_WR3.eps
07/02/2010
Rev. O