AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 21

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

Peak Detector
The peak detector always stores the input sample with the
largest magnitude. The absolute value of every input sample is
compared to what is currently in the peak detector’s holding
register. The only exception is when the control counter reaches
0; at this point, the dc offset estimate is updated and the peak
detector is set to the current input magnitude. The output of
each of the peak detectors is then encoded into a digital word
that represents the signal power in 6 dB steps relative to full
scale (FS).
DC Accumulator
The dc accumulator accumulates the 24-bit samples input from
the RCF filter until the control counter reaches 0. At this time,
the dc estimate in the holding register is updated, and the
accumulator is directly loaded with the new input sample to
begin work on the next estimate.
Control Counter
This counter controls the update of the dc correction block
based on the peak detector value and the input control registers.
The following three conditions are possible:
•
•
•
The integration period is given by Equation 15 and Equation 16.
The factor of 2 in the exponent shows that as peak signal power
increases, the integration time is increased by a factor of 4. This
decreases the bandwidth of the estimation filter, thus providing
the additional processing gain in the dc estimation term.
When the desired signal power equals the upper threshold,
When the desired signal power is less than the upper threshold,
If the digital word from the peak detector indicates that the
desired signal is below the lower threshold, the counter
merely cycles through at the minimum period.
If the digital word from the peak detector indicates that the
desired signal is above the upper threshold, the control
counter is held at the minimum period value and does
not count down; therefore, no update is made. When the
signal returns below the upper threshold, this counter
resumes counting.
If the digital word from the peak detector indicates that the
desired signal is between the lower threshold and the upper
threshold, the fine dc correction circuit is in its normal mode
of operation. In this mode, the control counter starts with the
minimum period but is reloaded with 4× minimum period
every time the peak detector output words increment by
6 dB. This errs on the side of caution and ensures that the
dc correction integrates long enough to obtain a valid
estimate. If smaller integrations are preferred, the minimum
period can be decreased or the lower threshold can be raised.
I
_
P
=
2
Min
_
Period
+
Ceil
⎛
⎜
⎜
⎝
Upper
_
Threshold
. 6
−
02
Lower
_
Threshold
⎞
⎟
⎟
⎠
×
2
(15)
Rev. A | Page 21 of 44
where Min_Period, Upper_Threshold, and Lower_Threshold are
register-programmable values.
To calculate the time required for the fine dc correction to
converge, use the following equation:
where:
T
Fine_DC_Converge is expressed in minutes, and for a GSM
application with 1× oversampling, it is 3.69 × 10
USER-CONFIGURABLE BUILT-IN SELF-TEST (BIST)
The AD6650 includes a BIST to assess digital functionality. This
feature verifies the integrity of the main digital signal paths of
the AD6650. Each BIST register is independent, meaning that
each channel can be tested independently at the same time.
The BIST is a thorough test of the selected AD6650 digital
signal path. With this test mode, it is possible to use the internal
pseudorandom generator to produce known test data. A
signature register follows the fine dc correction block. This
register can be read back and compared to a known good
signature. If the known good signature matches the register
value, the channel is fully operational.
If an error is detected, each internal block can be bypassed and
another test can be run to debug the fault. The I and Q paths are
tested independently. Use the following steps to perform this test:
1.
2.
3.
4.
5.
6.
7.
SYM
is the output symbol rate of the AD6650.
Reset the AD6650.
Program the desired AD6650 channel parameters for the
desired application (these parameters include decimation
rates, scalars, and RCF coefficients). Also, ensure that the
start holdoff counter is set to a nonzero value.
Set Register 0xA, Bit 1, to 1 (PN_EN).
Set Register 0x21, Bit 8, to 0 (fine DCC to BIST).
Start the A and/or B channels with a microprocessor write
(Soft_SYNC) or a pulse on the SYNC pin (Pin_SYNC).
Wait at least 300 μs.
Read the four BIST registers and compare the values to a
known good device. This ensures that the AD6650 is
programmed correctly and that each channel is
functioning correctly.
I
Fine
_
P
=
_
2
Min
DC
_
Period
_
Converge
+
Ceil
⎛
⎜
⎜
⎝
Desired
=
_
I
Signal
_
P
60
×
_
T
Power
SYM
. 6
02
−
Lower
−6
_
.
Threshold
AD6650
⎞
⎟
⎟
⎠
(16)
(17)
×
2