AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 5

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

ELECTRICAL CHARACTERISTICS
Table 3.
Parameter (Conditions)
LOGIC INPUTS
CLOCK INPUTS
LOGIC OUTPUTS
IDD SUPPLY CURRENT
POWER DISSIPATION
1
GENERAL TIMING CHARACTERISTICS
Table 4.
Parameter (Conditions)
CLK TIMING REQUIREMENTS
RESET TIMING REQUIREMENTS
PIN_SYNC TIMING REQUIREMENTS
SERIAL PORT TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS
1
2
All ac specifications are tested by driving CLK and CLK differentially.
Minimum specification is based on a 104 MSPS clock rate (an internal divide-by-2 must be used with a 104 MSPS clock rate); maximum specification is based on a
52 MSPS clock rate. This device is optimized to operate at a clock rate of 52 MSPS or 104 MSPS.
The timing parameters for SCLK, SDFS, SDO0, SDO1, and DR apply to both Channel 0 and Channel 1.
Logic Compatibility
Digital Logic
Input Capacitance
Differential Input Voltage
Common-Mode Input Voltage
Differential Input Resistance
Differential Input Capacitance
Logic Compatibility
Logic 1 Voltage (I
Logic 0 Voltage (I
CLK = 52 MHz (GSM Example)
CLK = 52 MHz (GSM/EDGE Example)
CLK Period
CLK Width Low
CLK Width High
RESET Width Low
SYNC to ↑ CLK Setup Time
SYNC to ↑ CLK Hold Time
↑ CLK to ↑ SCLK Delay (Divide-by-1)
↑ CLK to ↑ SCLK Delay (For Any Other Divisor)
↑ CLK to ↓ SCLK Delay (Divide-by-2 or Even Number)
↓ CLK to ↓ SCLK Delay (Divide-by-3 or Odd Number)
↑ SCLK to SDFS Delay
↑ SCLK to SDO0 Delay
↑ SCLK to SDO1 Delay
↑ SCLK to DR Delay
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
I
I
DVDD
AVDD
1
OH
OL
= 0.25 mA)
= 0.25 mA)
1
Temp
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
Full
Full
Full
Full
Full
Rev. A | Page 5 of 44
Test Level
IV
IV
IV
V
V
V
V
V
V
V
IV
IV
VII
VII
VII
2
t
t
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
CLK
CLKL
CLKH
SSF
SS
HS
DSCLK1
DSCLKH
DSCLKL
DSCLKLL
DSDFS
DSDO0
DSDO1
DSDR
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
2.0
0
0.4
2.4
Test Level
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
Typ
3.3 V CMOS
60
7
5
DVDD/2
7.5
5
3.3 V CMOS/TTL
VDD − 0.2
0.2
155
360
1.7
Min
9.6
30
−3
6
3.2
4.4
4.7
4
1
0.5
0.5
1
Typ
0.5 × t
0.5 × t
Max
VDD
0.8
3.6
0.8
2.1
CLK
CLK
AD6650
Max
19.2
12.5
16
16
14
2.6
3.5
3.5
3.5
Unit
V
V
μA
μA
pF
V p-p
V
kΩ
pF
V
V
mA
mA
W
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns