AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 26

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

AD6650
APPLICATION INFORMATION
REQUIRED SETTINGS AND START-UP SEQUENCE
FOR DC CORRECTION
On startup, the fine dc correction block may take up to several
minutes to converge to a good dc estimate, especially if a large
signal is present on the input. To improve this convergence
without run-time trade-offs, use a two-step start-up process.
The first step is to configure the fine dc correction block with
the parameters shown in Table 12. The freeze is set so that the
fine dc correction responds after the coarse dc correction has
updated. At the same time, the minimum period can be set to a
small value, such as 10. This guarantees a quicker convergence
because the minimum period is smaller, resulting in a smaller
integration period.
Also, setting the registers as described in Table 12, and
subsequently programming the AD6650, ensures that the VGA
and mixer are powered down during the power-on calibration
to keep signals with large dc content from interfering with the
estimation of the dc component from the analog path.
After ~500 ms, the freeze bit (Address 0x0B, Bit 0) can be
written low. The dc correction then converges and begins
removing the offset. If desired, the minimum period can
then be set to a larger value.
If the VGA and mixer are not disabled during a power-up using the
AutoCalibration control register as recommended, approximately
30 dB of suppression can be achieved, but the user must
guarantee that significant content is not present at the IF
frequency that will be translated to dc. If enhanced performance
is desired from the coarse dc correction, an RF switch or other
device can be used to shut off the input of the AD6650 until the
correction has been completed.
Table 12. DC Correction Register Recommendations
Description
AutoCalibration Control Register
AutoCalibration Control Register
AutoCalibration Control Register
AutoCalibration Control Register
Upper Threshold
Lower Threshold
Minimum Period
Freeze
Channel Address
0x22
0x22
0x22
0x22
0x0B
0x0B
0x0B
0x0B
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Bit
Bit 0
Bit 1
Bit 2
Bit 3
Bit 19 to Bit 13
Bit 12 to Bit 8
Bit 7 to Bit 3
Bit 0
Overall DC Correction Performance
With the recommended settings, the dc correction performance
is approximately −120 dBFS or better for small signals. Once the
signal is large enough to trip the AGC loop, the dc component
also rises; however, this component has been shown to always
be 40 dBc below the signal of interest. Therefore, the carrier-to-
dc ratio degrades for small signals. For additional details on the
dc correction registers, see the associated bit descriptions in the
Register Map section.
CLOCKING THE AD6650
The AD6650 encode signal must be a high quality, low phase
noise source to prevent degradation of performance. The
AD6650 can be clocked with a single-ended signal, but CLK
must be ac-coupled to ground. For optimum performance, the
AD6650 must be clocked differentially. The encode signal
should be ac-coupled into the CLK and CLK pins via a
transformer or capacitors. These pins are biased internally and
require no additional bias.
Figure 36 shows the preferred method for clocking the AD6650.
The clock source (low jitter) is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD6650 to approximately 0.8 V p-p differential. This
helps prevent large voltage swings of the clock from feeding
through to other portions of the AD6650 and limits the noise
presented to the encode inputs.
SOURCE
CLOCK
Figure 36. Crystal Clock Oscillator—Differential Encode
Value
Enabled (1)
Power down DACs at startup (0)
Enabled (1)
Sync ADCs (0)
−48 dBFS
−90 dBFS
+10 sample periods
Enabled (1)
0.1µF
T1-4T
0.01µF
HSMS2812
DIODES
CLK
CLK
AD6650