AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 24

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

AD6650
value is −40 dBFS. When the wideband signal is below the SPB
level, the FD loop is activated. This loop overrides the slow loop
and has a programmable step size (default 0.094 dB) and a
programmable peak detect period (defaults four samples at
1.08 MHz).
SERIAL OUTPUT DATA PORT
The AD6650 has two configurable serial output ports (SDO0
and SDO1). Both ports must be identically configured and are
programmed using the same control register. The ports share a
common SFDS, SCLK, and DR pin for connection to an
external ASIC or DSP; therefore, the outputs cannot be
programmed independently.
Serial Output Data Format
The AD6650 utilizes a twos complement data format with a
selectable serial data-word length of 16 bits or 24 bits. The data
is shifted out of the device in MSB-first format.
Serial Data Frame Sync
The serial data frame sync (SDFS) pin signals the start of the
serial data frame. As channel data becomes available at the
output of the AD6650’s filters, this data is transferred into the
serial data buffer. The internal serial controller initiates the
SDFS on the next rising edge of the serial clock. In the AD6650,
there are three modes in which the frame sync can be
generated, which are described in the SDFS Modes section.
Configuring the Serial Ports
Both serial output ports must function as master serial ports. A
serial bus master provides SCLK and SDFS outputs. Serial Port 0
and Serial Port 1 must be programmed as the bus masters by
setting Bit 3 of the serial control register high.
Serial Port Data Rate
The SCLK frequency is defined by Equation 21.
where:
f
SDIV is the serial division word for the channel.
~–1dBFS
–46dBFS
CLK
–6dBFS
is the frequency of the master clock of the AD6650 channel.
f
NOTES
1
2
3
SCLK
OPERATIONAL
ADJUSTABLE LEVEL, ADJUSTABLE STEP SIZE.
ADJUSTABLE LEVEL, WITH PROGRAMMABLE STEP SIZE AND ADJUSTABLE PERIOD.
ADJUSTABLE LEVEL, LOOP GAIN (<1), HYSTERESIS, INTEGRATION PERIOD.
RANGE
=
SDIV
f
CLK
(DEEP FADE PROTECTION)
REQUESTED LEVEL
LOWER THRESHOLD
+
Figure 31. AGC Thresholds
1
(OVER LOAD PROTECTION)
UPPER THRESHOLD
2
3
1
(21)
Rev. A | Page 24 of 44
The SDIV for Serial Port 0 and Serial Port 1 can be programmed
via Internal Control Register 0x21. Valid SDIV values are between
0 and 7, corresponding to divide ratios between 1 and 8.
Serial Output Frame Timing
The SDFS signal transitions high to signal the start of a data
frame. On the next rising edge of SCLK, the port drives the first
bit of the serial data on the SDO pin. The falling edge of SCLK
or the subsequent rising edge can then be used by the DSP to
sample the data until the required number of bits is received
(determined by the serial output port word length). If the DSP
has the ability to count bits, it can identify when the complete
frame is received.
Serial Port Timing Specifications
Figure 32 to Figure 35 indicate the timing required for the
AD6650 serial port.
SCLK
SCLK
SCLK
SCLK
SCLK is an output on the AD6650. All outputs are switched on
the rising edge of SCLK. The SDFS pin is sampled on the falling
edge of SCLK. This allows the AD6650 to recognize the SDFS in
time to initiate a frame on the next SCLK rising edge. The
maximum speed of this port is 52 MHz.
SDFS
SDO
CLK
SCLK
SDO
Figure 34. Serial Output Data Switching Characteristics
Figure 33. SCLK Switching Characteristics (Divide-by-1)
RISING SCLK AFTER SDFS GOES HIGH
FIRST DATA IS AVAILABLE THE FIRST
Figure 35. Timing for Serial Output Port
Figure 32. SCLK Timing Requirements
t
DSCLKH
t
SCLKL
t
DSDO
t
SCLKL
t
t
I
SCLKH
SCLK
15
t
DSO
t
SCLKH
I
14
I
MSB
SDFS MINIMUM
WIDTH IS ONE SCLK
I
13
I
MSB1