AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 39

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

REGISTER DETAILS
Table 19. PLL Register 0: Control Latch
CH Address
DB21 to DB0
Table 20. PLL Register 1: R Counter Latch
CH Address
DB21 to DB14
DB13 to DB0
Table 21. PLL Register 2: N Counter Latch
CH Address
DB21 to DB19
DB18 to DB6
DB5
DB4 to DB0
Table 22. PLL Register 3—Reserved
CH Address
DB21 to DB0
0x00: Clock Divider Control [1]
The clock divider control bit sets the internal clock rate for the
AD6650. If this bit is set low and the clock rate is ≤52 MSPS, the
internal divide-by-2 is bypassed. If a faster clock rate is desired,
the clock divider control bit should be set high. By setting this
bit high, the internal divide-by-2 is used.
0x01: PLL Control Register 0 [21:0]
This register is reserved and must be written 00 0000 0111 1100
0100 0000 (MSB ... LSB).
0x02: PLL Control Register 1 [21:0]
DB13 to DB0: These bits are used to set the R-counter for the PLL.
DB21 to DB14: These bits are reserved and must be written
0001 0100.
0x03: PLL Control Register 2 [21:0]
DB4 to DB0: This 5-bit register is used to set the value for the A
counter in the PLL.
DB5: This bit is reserved and must be written to 0.
DB18 to DB6: This 13-bit register is used to set the value for the
B-counter in the PLL.
DB21 to DB19: These bits are reserved and must be written 000.
0x04: PLL Control Register 3 [21:0]
This register is reserved and must be written 11 0001 1000 0000
0000 0000 (MSB ... LSB).
Register
RSVD
B13 to B1
RSVD
A5-A1
Register
RSVD
Register
RSVD
Register
RSVD
R1 to R14
Description
Reserved
13-bit B counter
Reserved
5-bit A counter
Description
Reserved
Bit Definitions
Reserved
Description
Reserved
14-bit reference counter, R
Comment
Must be written 000.
Must be written 0.
A5 to A1 programs the 5-bit counter. The divide range is 0 (00000) to 31 (11111).
B13 to B1 programs the 13-bit B counter.
Comment
Must be written 00 0000 0111 1100 0100 0000 (MSB ... LSB).
Comment
Must be written 11 0001 1000 0000 0000 0000 (MSB ... LSB).
Rev. A | Page 39 of 44
0x05: Clamp Control [5:0]
This register either enables or disables the clamps on the output
of the mixers. These clamps should be enabled.
0x06: Reserved [8:0]
This register is reserved and must be written 00000000.
0x07: Reserved [8:0]
This register is reserved and must be written 00000000.
0x08: Reserved [8:0]
This register is reserved and must be written 00010001.
0x09: Reserved [1:0]
This register is reserved and should be written low.
Comment
Must be written 0001 0100 (DB21 ... DB14).
AD6650