AD6650ABCZ Analog Devices Inc, AD6650ABCZ Datasheet - Page 23

• Manufacturer Part Number: AD6650ABCZ
• Description: DIVERSITY IF-TO-BASEBAND GSM/EDGE NARROW-BAND RECEIVER
• Manufacturer: Analog Devices Inc

CP OUTPUT
LDO
The AD6650 includes an on-chip 2.6 V low dropout (LDO)
voltage regulator that supplies the VCO and other sections of
the PLL. A 0.22 μF bypass capacitor is required on the VLDO
output to ensure stability. This LDO employs the same technology
used in the anyCAP® line of regulators from Analog Devices, Inc.,
making it insensitive to the type of capacitor used. Driving an
external load from the VLDO output is not supported.
AGC LOOP/RELINEARIZATION
The AGC consists of three gain control loops: a slow loop, a fast
attack (FA) loop, and a fast decay (FD) loop.
R-DIVIDER
N-DIVIDER
R-DIVIDER
N-DIVIDER
Figure 29. PFD Simplified Schematic and Timing (Locked)
THRESHOLD
LF
MACHINE
UPPER
AD6650
STATE
HI
HI
AGC
Figure 30. AGC Loop Block Diagram
D1
D2
VLDO
CLR1
CLR2
CP
FAST LOOP DETECTORS
U1
U2
Figure 28. Loop Filter Circuit
Q1
Q2
ADP2
UP
DOWN
ADP1
200Ω
1.0µF
U3
SIGNAL PLUS BLOCKER LEVEL
SLOW LOOP, SIGNAL LEVEL
56000pF
ADC
ADC
867Ω
CPGND
V
P
CHARGE
PUMP
3900pF
CP
Rev. A | Page 23 of 44
Slow Loop
The slow loop is the main loop and is associated with a loop
gain parameter. This parameter controls the rate of change of
the gain and should always be less than 1. To determine the
loop gain, Equation 19 should be used.
where:
K
K
As the loop gain value increases, the speed of the response of
the AGC loop increases; as the loop gain value decreases, so
does the speed of the response of the AGC loop. The slow loop
attempts to maintain the signal entering the ADC at a given
level, referred to as the requested level. This level is specified in
dBFS and can be between 0 dBFS and −24 dBFS (in 0.094 dB
steps) of the converter resolution. The default value is −6.02 dBFS.
The slow loop has a peak detection function, the period of
which can be set by the user. This period should be set to ¼ of
the symbol period, or greater, to prevent the AGC loop from
gaining off the envelope of the EDGE signal. This detection
period works because the peak detector’s operation is based on
dB (max(|I|, |Q|)); therefore, all of the I/Q samples are reflected
back into one quadrant of the I/Q plane. At a 26 MHz sampling
frequency, one symbol period is 96 clock cycles. Therefore, to
obtain a peak detector period that is ¼ of the symbol period,
the peak detector period should be set to a minimum of 24
samples. The following equation can also be used:
where:
f
f
Fast Attack (FA) Loop
The FA loop utilizes an analog threshold detector that prevents
overdrive of the analog signal path. In a situation that could
potentially overdrive the ADC, the FA loop takes over from the
slow loop and decreases the gain to the VGA in the front end.
The step size used for the FA loop is programmable between
0 dB and 1.504 dB in 0.094 dB steps. The FA loop also has a
counter that is programmable between 1 and 16. When
initialized to count + 1, the FA loop decreases the gain for
count + 1 clock cycles when the threshold is crossed.
Fast Decay (FD) Loop
The FD loop is a fast loop that increases the gain when the
signal falls below a threshold during a deep channel fade or on
the ramp down. The fast loop accomplishes this task by
comparing the peak signal-plus-blocker level at the ADC output
(which includes the signal and any blockers that pass through
the SAW filter) with a programmable level (SPB_level) that
determines when this loop is activated. The SBP_level default
SYM
SAMP
Mantissa
Exponent
= 270.833 kHz (GSM symbol rate).
= 26 MHz.
AGCLoopGai
SPB
is the loop gain mantissa. Values can range from 0 to 63.
is the loop gain exponent. Values can range from 0 to 7.
Peak
Samples
n
=
⎛
⎜
⎝
K
≥
Mantissa
256
1
4
×
(
f
SAMP
⎞
⎟
⎠
×
2
/
−
K
f
SYM
Exponent
)
AD6650
(19)
(20)