PIC18F1220-H/ML Microchip Technology, PIC18F1220-H/ML Datasheet - Page 303
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F1220-H/ML
Manufacturer Part Number
PIC18F1220-H/ML
Description
IC MCU 8BIT 4KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1220-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Timing Diagrams and Specifications ................................ 257
© 2007 Microchip Technology Inc.
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 261
Transition for Entry to SEC_IDLE Mode .................... 24
Transition for Entry to SEC_RUN Mode .................... 26
Transition for Entry to Sleep Mode ............................ 22
Transition for Two-Speed Start-up
Transition for Wake from PRI_IDLE Mode ................. 23
Transition for Wake from RC_RUN Mode
Transition for Wake from SEC_RUN Mode
Transition for Wake from Sleep (HSPLL) ................... 22
Transition to PRI_IDLE Mode .................................... 23
Transition to RC_IDLE Mode ..................................... 25
Transition to RC_RUN Mode ..................................... 27
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ................................... 259
EUSART Synchronous Receive Requirements ....... 264
EUSART Synchronous
External Clock Requirements .................................. 257
Internal RC Accuracy ............................................... 258
PLL Clock, HS/HSPLL Mode
Reset, Watchdog Timer, Oscillator
Timer0 and Timer1 External Clock
(MCLR Tied to V
(MCLR Not Tied to Vdd), Case 1 ....................... 39
(MCLR Not Tied to Vdd), Case 2 ....................... 39
(MCLR Tied to Vdd, Vdd Rise pwrt) ................... 39
(INTOSC to HSPLL) ......................................... 181
(RC_RUN to PRI_RUN) ..................................... 25
(HSPLL) ............................................................. 24
(All CCP Modules) ........................................... 263
Transmission Requirements ............................ 263
(V
Start-up Timer, Power-up Timer and
Brown-out Reset Requirements ....................... 261
Requirements ................................................... 262
DD
= 4.2V to 5.5V) ........................................ 258
DD
) ........................................... 40
Top-of-Stack Access .......................................................... 42
TSTFSZ ........................................................................... 231
Two-Speed Start-up ..................................................171, 181
Two-Word Instructions ....................................................... 46
TXSTA Register
W
Watchdog Timer (WDT) ............................................171, 180
WWW Address ................................................................ 302
WWW, On-Line Support ...................................................... 4
X
XORLW ............................................................................ 231
XORWF ........................................................................... 232
Example Cases .......................................................... 46
BRGH Bit ................................................................. 135
Associated Registers ............................................... 181
Control Register ....................................................... 180
During Oscillator Failure .......................................... 182
Programming Considerations .................................. 180
PIC18F1220/1320
DS39605F-page 301
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