PIC18F1220-H/ML Microchip Technology, PIC18F1220-H/ML Datasheet - Page 37
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F1220-H/ML
Manufacturer Part Number
PIC18F1220-H/ML
Description
IC MCU 8BIT 4KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1220-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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TABLE 4-1:
REGISTER 4-1:
TABLE 4-2:
© 2007 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
Power-on Reset
RESET Instruction
Brown-out
MCLR during Power Managed
Run modes
MCLR during Power Managed
Idle modes and Sleep
WDT Time-out during Full
Power or Power Managed Run
MCLR during Full Power
Execution
Stack Full Reset (STVR = 1)
Stack Underflow Reset
(STVR = 1)
Stack Underflow Error (not an
actual Reset, STVR = 0)
WDT Time-out during Power
Managed Idle or Sleep
Interrupt Exit from Power
Managed modes
Legend: u = unchanged, x = unknown, – = unimplemented bit, read as ‘0’
Note 1:
Configuration
2: 2 ms is the nominal time required for the 4x PLL to lock.
3: The program memory bias start-up time is always invoked on POR, wake-up from Sleep, or on any exit
Oscillator
from power managed mode that disables the CPU and instruction execution.
Condition
When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
TIME-OUT IN VARIOUS SITUATIONS
STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
RCON REGISTER BITS AND POSITIONS
bit 7
Note:
R/W-0
IPEN
66 ms
66 ms
(1)
Refer to Section 5.14 “RCON Register” for bit definitions.
PWRTEN = 0
+ 1024 T
Program
Counter
(1)
PC + 2
PC + 2
66 ms
66 ms
66 ms
0000h
0000h
0000h
0000h
0000h
0000h
0000h
0000h
U-0
—
+ 1024 T
Power-up
OSC
(1)
(1)
(1)
+ 2 ms
OSC
0--1 1100
0--0 uuuu
0--1 11u-
0--u 1uuu
0--u 10uu
0--u 0uuu
0--u uuuu
u--u uuuu
u--u 00uu
u--u u0uu
U-0
Register
—
RCON
(2)
(2)
and Brown-out
R/W-1
RI
RI
1024 T
1
0
1
u
u
u
u
u
u
u
PWRTEN = 1
1024 T
TO
5-10 μs
5-10 μs
5-10 μs
1
u
1
1
1
0
u
u
0
u
OSC
PIC18F1220/1320
R/W-1
TO
PD
+ 2 ms
OSC
1
u
1
u
0
u
u
u
0
0
(3)
(3)
(3)
POR
(2)
0
u
u
u
u
u
u
u
u
u
R/W-1
PD
BOR
0
u
0
u
u
u
u
u
u
u
1024 T
Low-Power Mode
STKFUL
R/W-1
POR
1024 T
Exit from
5-10 μs
5-10 μs
5-10 μs
0
u
u
u
u
u
u
1
u
u
u
u
DS39605F-page 35
OSC
+ 2 ms
OSC
(3)
(3)
(3)
STKUNF
R/W-1
BOR
0
u
u
u
u
u
u
u
1
1
u
u
(2)
bit 0
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