PIC18F1320-H/ML Microchip Technology, PIC18F1320-H/ML Datasheet - Page 215
PIC18F1320-H/ML
Manufacturer Part Number
PIC18F1320-H/ML
Description
IC MCU 8BIT 8KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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INCFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2007 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
PC
If CNT
PC
Q1
Q1
Q1
No
No
No
=
=
=
=
≠
=
register ‘f’
operation
operation
operation
Increment f, skip if 0
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest,
skip if result = 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is ‘0’, the next instruc-
tion, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction. If ‘a’ is ‘0’, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
NZERO
ZERO
Read
0011
Q2
Q2
Q2
No
No
No
Address (HERE)
CNT + 1
0;
Address (ZERO)
0;
Address (NZERO)
by a 2-word instruction.
INCFSZ
:
:
INCFSZ
11da
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
ffff
f [,d [,a]]
CNT
destination
operation
operation
operation
Write to
Q4
Q4
Q4
No
No
No
ffff
INFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
REG
If REG
PC
If REG
PC
PIC18F1220/1320
Q1
Q1
Q1
No
No
No
=
=
≠
=
=
=
register ‘f’
operation
operation
operation
Increment f, skip if not 0
[ label ]
0 ≤ f ≤ 255
d ∈ [0,1]
a ∈ [0,1]
(f) + 1 → dest,
skip if result ≠ 0
None
The contents of register ‘f’ are
incremented. If ‘d’ is ‘0’, the result
is placed in W. If ‘d’ is ‘1’, the result
is placed back in register ‘f’
(default).
If the result is not ‘0’, the next
instruction, which is already
fetched, is discarded and a NOP is
executed instead, making it a
two-cycle instruction. If ‘a’ is ‘0’, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
1
1(2)
Note: 3 cycles if skip and followed
HERE
ZERO
NZERO
Read
0100
Q2
Q2
Q2
No
No
No
Address (HERE)
REG + 1
0;
Address (NZERO)
0;
Address (ZERO)
by a 2-word instruction.
INFSNZ REG
INFSNZ
10da
operation
operation
operation
Process
Data
Q3
Q3
Q3
No
No
No
DS39605F-page 213
ffff
f [,d [,a]]
destination
operation
operation
operation
Write to
Q4
Q4
Q4
No
No
No
ffff
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