PIC18F1320-H/ML Microchip Technology, PIC18F1320-H/ML Datasheet - Page 73
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PIC18F1320-H/ML
Manufacturer Part Number
PIC18F1320-H/ML
Description
IC MCU 8BIT 8KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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8.0
8.1
An 8 x 8 hardware multiplier is included in the ALU of
the PIC18F1220/1320 devices. By making the multiply
a hardware operation, it completes in a single instruc-
tion cycle. This is an unsigned multiply that gives a
16-bit result. The result is stored into the 16-bit product
register pair (PRODH:PRODL). The multiplier does not
affect any flags in the Status register.
TABLE 8-1:
8.2
Example 8-1 shows the sequence to do an 8 x 8
unsigned multiply. Only one instruction is required
when one argument of the multiply is already loaded in
the WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiply. To account for the sign bits of the arguments,
each argument’s Most Significant bit (MSb) is tested
and the appropriate subtractions are done.
EXAMPLE 8-1:
© 2007 Microchip Technology Inc.
8 x 8 unsigned
8 x 8 signed
16 x 16 unsigned
16 x 16 signed
MOVF
MULWF
Routine
8 x 8 HARDWARE MULTIPLIER
Introduction
Operation
ARG1, W
ARG2
PERFORMANCE COMPARISON
Without hardware multiply
Without hardware multiply
Without hardware multiply
Without hardware multiply
8 x 8 UNSIGNED
MULTIPLY ROUTINE
;
; ARG1 * ARG2 ->
; PRODH:PRODL
Hardware multiply
Hardware multiply
Hardware multiply
Hardware multiply
Multiply Method
Program
Memory
(Words)
13
33
21
28
52
35
1
6
Making the 8 x 8 multiplier execute in a single cycle
gives the following advantages:
• Higher computational throughput
• Reduces code size requirements for multiply
The performance increase allows the device to be used
in applications previously reserved for Digital Signal
Processors.
Table 8-1 shows a performance comparison between
Enhanced devices using the single-cycle hardware
multiply and performing the same function without the
hardware multiply.
EXAMPLE 8-2:
MOVF
MULWF
BTFSC
SUBWF
MOVF
BTFSC
SUBWF
algorithms
Cycles
(Max)
242
254
69
91
28
40
1
6
PIC18F1220/1320
ARG1, W
ARG2
ARG2, SB
PRODH, F
ARG2, W
ARG1, SB
PRODH, F
@ 40 MHz
24.2 μs
25.4 μs
100 ns
600 ns
6.9 μs
9.1 μs
2.8 μs
4 μs
8 x 8 SIGNED MULTIPLY
ROUTINE
; ARG1 * ARG2 ->
; PRODH:PRODL
; Test Sign Bit
; PRODH = PRODH
;
; Test Sign Bit
; PRODH = PRODH
;
@ 10 MHz
102.6 μs
27.6 μs
36.4 μs
96.8 μs
11.2 μs
Time
400 ns
2.4 μs
16 μs
- ARG1
- ARG2
DS39605F-page 71
@ 4 MHz
242 μs
254 μs
69 μs
91 μs
28 μs
40 μs
1 μs
6 μs
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