82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 17

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
INDUSTRIAL TEMPERATURE RANGE
† Notes:
Voltages are with respect to ground (V
) unless otherwise stated.
SS
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1. Fref0 reference input selected.
2. Fref1 reference input selected.
3. Normal Mode selected.
4. Holdover Mode selected.
5. Freerun Mode selected.
6. 8 kHz Frequency Mode selected.
7. 1.544 MHz Frequency Mode selected.
8. 2.048 MHz Frequency Mode selected.
9. Master clock input OSCi at 20 MHz ±0 ppm.
10. Master clock input OSCi at 20 MHz ±32 ppm.
11. Master clock input OSCi at 20 MHz ±100 ppm.
12. Selected reference input at 0 ppm.
13. Selected reference input at 32 ppm.
14. Selected reference input at 100 ppm.
15. For Freerun Mode of 0 ppm.
16. For Freerun Mode of 32 ppm.
17. For Freerun Mode of 100 ppm.
18. For capture range of 230 ppm.
19. For capture range of 198 ppm.
20. For capture range of 130 ppm.
21. 25 pF capacitive load.
22. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
23. Jitter on reference input is obtained at slightly higher input jitter amplitudes.
24. Applied jitter is sinusoidal.
25. Minimum applied input jitter magnitude to regain synchronization.
26. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
27. Within 10 ms of the state, reference or input change.
28. 1 UIpp = 125 s for 8 kHz signals.
29. 1 UIpp = 648 ns for 1.544 MHz signals.
30. 1 UIpp = 488 ns for 2.048 MHz signals.
31. 1 UIpp = 323 ns for 3.088 MHz signals.
32. 1 UIpp = 244 ns for 4.096 MHz signals.
33. 1 UIpp = 122 ns for 8.192 MHz signals.
34. 1 UIpp = 61 ns for 16.484 MHz signals.
35. 1 UIpp = 30 ns for 32.968 MHz signals.
36. No filter.
37. 40 Hz to 100 kHz bandpass filter.
38. With respect to reference input signal frequency.
39. After a RST or TCLR.
40. Master clock duty 40% to 60%.
41. Prior to Holdover Mode, device as in Normal Mode and phase locked.
42. With input frequency offset of 100 ppm.
17