82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 9

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
to the Digital Control Oscillator, at which a E1, T1 and C6 signals are
generated.
Fraction Block
and Fraction_T1 blocks generate C6 and T1 signals, respectively.
Digital Control Oscillator (DCO)
from Loop Filter or Fraction blocks. Based on the values of the received
signals, the DCO generates three digital outputs: 25.248 MHz, 32.768
MHz and 24.704 MHz for C6, E1 and T1 dividers, respectively.
using storage techniques.
generated by OSC.
Lock Indicator
the input phase offset is small enough so that no slope limiting is exhibited,
the LOCK pin will be set high.
By applying some algorithms on the incoming E1 signal, the Fraction_C6
In Normal Mode, the DCO receives the three limited and filtered signals
In Holdover mode, the DCO is running with the signal generated by
In Freerun mode, the DCO is running with the master frequency signal
If the center frequency of the DPLL is identical to the line frequency, and
Loop Filter
Fraction_T1
Fraction_C6
Limiter
FLOCK
Figure 6. DPLL Block Diagram
Detector
Phase
25.248 MHz
32.768 MHz
24.704 MHz
Virtual Reference
9
Output Interface
generate total eight types of clock signals and six types of framing signals.
types of clock signals (C2o, C4o, C8o, C16o and C32o) with nominal 50%
duty cycle and six types of framing signals (F0o, F8o, F16o, F32o, RSP
and TSP).
types of T1 signals (C1.5o and C3o) with nominal 50% duty cycle.
C6o signal with nominal 50% duty cycle.
OSC
source.
to the frequency tolerance of the source at the OSCi pin. For applications
not requiring an accurate Freerun Mode, tolerance of the master timing
source may be ±100 ppm. For applications requiring an accurate Freerun
Mode, such as AT&T TR62411, the tolerance of the master timing source
Feedback
Signal
The Output Interface uses the three output signals of the DCO to
The 32.768 MHz signal is used by the E1_divider circuit to generate five
The 24.704 MHz signal is used by the T1_divider circuit to generate two
The 25.248 MHz signal is used by the C6_divider circuit to generate the
All these output signals are synchronous to F8o.
The IDT82V3002 can use either a clock or crystal as the master timing
In Freerun Mode, the frequency tolerance at the clock outputs is identical
Output Interface
C6_Divider
T1_Divider
E1_Divider
F_sel1 F_sel0
Frequency
Selection
Circuit
INDUSTRIAL TEMPERATURE RANGE
C1.5o
C3o
C2o
C4o
C8o
C16o
C32o
F0o
F8o
F16o
F32o
RSP
TSP
C6o