82V3002PVG8 IDT, Integrated Device Technology Inc, 82V3002PVG8 Datasheet - Page 4

• Manufacturer Part Number: 82V3002PVG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V3002PVG8

• Lead Free Status / Rohs Status: Compliant

IDT82V3002 WAN PLL WITH DUAL REFERENCE INPUTS
PIN DESCRIPTION (CONTINUED)
IC0, IC1, IC2
FREERUN
MON_out
Name
C1.5o
TRST
C32o
C16o
F32o
F16o
RSP
TDO
TCK
TMS
C8o
C4o
C2o
C3o
C6o
TSP
F8o
F0o
TDI
IC
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
(CMOS) O
Type
O
I
I
I
I
-
-
Pin Number
8, 21, 22, 34
53, 54, 55
35, 43
51
25
24
23
20
17
16
15
14
40
39
36
33
41
42
29
32
30
28
31
7
Freerun Indicator.
This output goes to a logic high whenever the DPLL goes into Freerun Mode.
Monitor Reference Out Of Capture Range.
A logic high at this pin indicates that the reference is off the nominal frequency by more than 12ppm.
Clock 32.768 MHz.
This output is used for ST-BUS operation with a 32.768 MHz clock.
Clock 16.384 MHz.
This output is used for ST-BUS operation with a 16.384 MHz clock.
Clock 8.192 MHz.
This output is used for ST-BUS operation with an 8.192 MHz clock.
Clock 4.096 MHz.
This output is used for ST-BUS operation with a 4.096 MHz clock.
Clock 2.048 MHz.
This output is used for ST-BUS operation with a 2.048 MHz clock.
Clock 3.088 MHz.
This output is used for T1 applications.
Clock 1.544 MHz.
This output is used for T1 applications.
Clock 6.312 MHz.
This output is used for DS2 applications.
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 31 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 8.192 Mb/s.
Frame Pulse ST-BUS 8.192 Mb/s.
This is an 8 kHz 61 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 8.192 Mb/s.
Frame Pulse.
This is an 8 kHz 122 ns active high framing pulse, which marks the beginning of a frame.
Frame Pulse ST-BUS 2.048 Mb/s.
This is an 8 kHz 244 ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for ST-BUS operation at 2.048 Mb/s and 4.096 Mb/s.
Receive Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of a ST-BUS frame. This is
typically used for connection to the Siemens MUNICH-32 device.
Transmit Sync Pulse.
This is an 8 kHz 488 ns active high framing pulse, which marks the beginning of an ST-BUS frame. This is
typically used for connection to the Siemens MUNICH-32 device.
Test Serial Data Out. JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in
high impedance state when JTAG scan is not enabled.
Test Serial Data In. JTAG serial test instructions and data are shifted in on this pin. This pin is internally
pulled up to V
Test Reset. Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state.
This pin is internally pulled up to V
Test Clock. Provides the clock to the JTAG test logic. This pin is internally pulled up to V
Test Mode Select. JTAG signal that controls the state transitions of the TAP controller. This pin is internally
pulled up to V
These pins should be connected to V
These pins should be left open.
DD
DD
.
.
4
DD
. It is connected to the ground for normal applications.
SS.
Description
INDUSTRIAL TEMPERATURE RANGE
DD
.