SC28C94A1A,518 NXP Semiconductors, SC28C94A1A,518 Datasheet - Page 12

• Manufacturer Part Number: SC28C94A1A,518
• Description: IC UART QUAD W/FIFO 52-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC28C94A1A,518

• Features: False-start Bit Detection
• Number Of Channels: 4, QUART
• Fifo's: 8 Byte
• Voltage - Supply: 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 52-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1114-2; 935262534518; SC28C94A1A-T

Philips Semiconductors
Arbitration - Aftermath
At the end of the arbitration, i.e., the falling edge of EVAL, the
winning interrupt source is driving its Channel number, number of
bytes (if applicable) and interrupt type onto the Interrupt Bus. These
values are captured into a latch by the trailing edge of EVAL. The
output of this latch is used by the Interrupt Threshold comparator;
the winning value is captured into another set of latches called the
Current Interrupt Register (CIR) at the time of an Interrupt
Acknowledge cycle or execution of the “Update CIR” command.
The Current Interrupt Register and associated read logic is shown in
Figure 8. Interrupting channel number and the three bit interrupt
type code and FIFO fill level are readable via the Internal Data Bus.
The contents of the appropriate receiver or transmitter byte
“counter”, as captured at the time of IACKN assertion, make up bits
7:5 of the CIR. If the interrupt type stored in the Current Interrupt
Register is not a receiver or transmitter data transfer type, the
CIR7:5 field will read as the programmable fields of their respective
bid formats.
The buffers driving the CIR to the DBUS also provide the means of
implementing the Global Interrupting Channel and Global Byte
Count Registers, described in a later section.
The winning bid channel number and interrupt type fields can also
be used to generate part of the Interrupt Vector, as defined by the
Interrupt Control Register.
Interrupt Context
The channel number of the winning “bid” is used by the address
decoders to provide data from the interrupting UART channel via a
set of Global pseudo-registers. The interrupt Global
pseudo-registers are:
The first two Global “registers” are provided by Current Interrupt
Register fields as shown in Figure 8. The interrupting channel
number latched in CIR modifies address decoding so that the
Receive or Transmit Holding Register for the interrupting channel is
accessed during I/O involving the Global Receive and Transmit
Holding Registers. Similarly, for data interrupts from the transmitter
and receiver, the number of characters available for transfer to the
CPU or the number of transmit FIFO positions open is available by
reading the Global Interrupt Byte Count Register. For non-data
interrupts, a read of the Global Interrupt Byte Count Register yields
a value equal to the highest programmable filed.
In effect, once latched by an IACK or the Update CIR command, the
winning interrupt channel number determines the contents of the
global registers. All Global registers will provide data from the
interrupting UART channel.
Interrupt Threshold Calculation
The state of IRQN is determined by comparison of the winning “bid”
value to the Interrupt Threshold field of the Interrupt Control
Register.
The logic of the bidding circuit is such that when no interrupt source
has a value greater than the interrupt threshold then the interrupt is
not asserted and the CIR (Current Interrupt Register) is set to all
2006 Aug 09
1. Global Interrupting Byte Count
2. Global Interrupting Channel
3. Global Receive Holding Register
4. Global Transmit Holding Register
Quad universal asynchronous receiver/transmitter (QUART)
12
ones. When one or more of the 18 interrupt sources which are
enabled via the IMR (Interrupt Mask Register) exceed the threshold
then the interrupt threshold is effectively disconnected from the
bidding operation while the 18 sources now bid against each other.
The final result is that the highest bidding source will disable all
others and its value will be loaded to the CIR and the IRQN pin
asserted low. This all occurs during each cycle of the X1, X2 crystal
clock.
Table 2. Receiver FIFO Interrupt Fill Level
For the receiver these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
receiver FIFO is empty. The default setting of these bits cause the
receiver to attempt to interrupt when it has one or more bytes in it.
Table 3. Transmitter FIFO Interrupt Fill Level
For the transmitter these bits control the number of FIFO positions
empty when the receiver will attempt to interrupt. After the reset the
transmit FIFO has 8 bytes empty. It will then attempt to interrupt as
soon as the transmitter is enabled. The default setting of the MR0
bits (00) condition the transmitter to attempt to interrupt only when it
is competely empty. As soon as one byte is loaded, it is no longer
empty and hence will withdraw its interrupt request.
*These conditions, for interrupt purposes, make the RxFIFO look
like a 3 byte FIFO; the TxFIFO a 1 byte FIFO. This is to allow
software compatibility with previous Philips UART devices. Both
FIFOs accept 8 bytes of data regardless of this bit setting. Only the
interrupt is affected.
INTERRUPT NOTE ON 28C94:
For the receivers and transmitters, the bidding of any particular
unit may be held off unless one of four FIFO fill levels is
attained. This is done by setting the RxINT and TxINT bits in
MR0 and MR1 to non-zero values. This may be used to prevent
a receiver or transmitter from generating an interrupt even
though it is filed above the bid threshold. Although this is not
in agreement with the idea that each enabled interrupt source
bid with equal authority, it does allow the flexibility of giving
particular receiver or transmitters more interrupt importance
than others.
This may be used when the Interrupt Threshold is set at or
above 100000. Note than in this case the transmitter cannot
generate an interrupt. If the interrupt threshold MSBs were set
to 011 and the ‘Receiver Interrupt Bits’ on the MR registers set
to a value other than 00 then the RxFIFO could not generate
and interrupt until it had 4, 6 or 8 bytes. This in effect partially
defeats the hardwired characteristic that the receiver interrupts
should have more importance than the transmitter. This
characteristic has been implemented by setting the MSB of the
transmitter bid to zero.
MR0[6]
MR0[5]
0
0
1
1
0
0
1
1
MR1[6]
MR0[4]
0
1
0
1
0
1
0
1
1 or more bytes in FIFO (Rx RDY) default*
3 or more bytes in FIFO
6 or more bytes in FIFO
8 bytes in FIFO (Rx FULL)
8 bytes empty (Tx EMPTY) default*
4 or more bytes empty
6 or more bytes empty
1 or more bytes empty (Tx RDY)
Interrupt Condition
Interrupt Condition
SC28C94
Product data sheet