MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet
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MAX3107ETG+
Specifications of MAX3107ETG+
Related parts for MAX3107ETG+
MAX3107ETG+ Summary of contents
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... Special_Character_Detection S GPIO-Based_Character_Detection S 9-Bit_Multidrop-Mode_Data_Filtering S SIR-_and_MIR-Compliant_IrDA_Encoder/Decoder S +2.35V_to_+3.6V_Supply_Range S Logic-Level_Translation_on_the_Controller_and_ S Transceiver_Interfaces_(Down_to_1.7V) Four_Flexible_GPIOs S Line_Noise_Indication S Shutdown_and_Autosleep_Modes S Low_640µA_(typ)_Supply_Current_at_1Mbaud_and_ S 20MHz_Clock Low_20µA_(typ)_Shutdown_Power S PART MAX3107EAG+ MAX3107ETG+ +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. Functional Diagram appears at end of data sheet. Features Ordering Information TEMP_RANGE PIN-PACKAGE -40NC to +85NC 24 SSOP -40NC to +85NC 24 TQFN-EP* ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPI/I TABLE OF CONTENTS (continued) Power-Up and IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator 2 Figure Timing Diagram ...
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SPI/I RHR—Receiver Hold Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator ABSOLUTE MAXIMUM RATINGS (Voltages referenced to AGND XIN ................................................ -0.3V to +4. EXT V , XOUT .................................................. -0. RST, ...
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SPI/I DC ELECTRICAL CHARACTERISTICS (continued +2.35V to +3.6V +1.71V to +3.6V are +2.8V +1.8V +2.5V EXT PARAMETER SYMBOL SCLK/SCL, DOUT/SDA DOUT/SDA Output Low ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator DC ELECTRICAL CHARACTERISTICS (continued +2.35V to +3.6V +1.71V to +3.6V are +2.8V +1.8V +2.5V ...
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SPI/I AC ELECTRICAL CHARACTERISTICS (continued +2.35V to +3.6V +1.71V to +3.6V are +2.8V +1.8V +2.5V EXT PARAMETER SYMBOL Data Setup Time t SU:DAT ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator START CONDITION (S) SDA t t HD:STA HD:DAT t SU:DAT SCL t HIGH 2 Figure Timing Diagram CS t CSS t CSH SCLK ...
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SPI 2.5V 2.5V 2.5V, LDOEN = EXT I SUPPLY CURRENT vs. V VOLTAGE A A (EXTERNAL CLOCK, PLL DISABLED) 140 EXTERNAL 3.6MHz CLOCK BAUD RATE = 115kbps 120 ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator TOP VIEW EXT 21 XOUT MAX3107 XIN 22 AGND (3.5mm × 3.5mm) *CONNECT EP TO AGND. PIN ...
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SPI/I PIN NAME TQFN-EP SSOP 7 10 DIN/ IRQ 9 12 RST DGND 12 15 GPIO0 13 16 GPIO1 14 17 GPIO2 15 18 GPIO3 16 19 CTS 17 20 RTS/CLKOUT 18 ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator (All default reset values are 0x00, unless otherwise noted. All registers are R/W, unless otherwise noted.) REGISTER ADDR BIT 7 FIFO DATA RHR † 0x00 RData7 THR † 0x00 TData7 ...
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SPI/I Detailed Description The MAX3107 UART is a bridge between an SPI/ 2 MICROWIRE™ microprocessor bus and an asynchronous serial-data communication link, such as RS-485, RS-232, or IrDA. The MAX3107 contains an advanced UART, a fractional baud-rate ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator LSB RECEIVED DATA START D0 MIDDATA SAMPLING Figure 4. Receive Data Format RX A BAUD BLOCK Figure 5. Midbit Sampling To halt transmission, set MODE1[1]: TxDisabl to ...
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SPI/I RECEIVER OVERRUN LSR[1] WORD TRIGGER ISR[3] FIFOTrgLvl[7:4] RECEIVE FIFO CURRENT FILL LEVEL RxFIFOLvl 2 I C/SPI INTERFACE TIMEOUT LSR[0] EMPTY ISR[6] ERRORS LSR[5:2] Figure 6. Receive FIFO The internal 614.4kHz oscillator does not require exter- nal components and provides ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator The integer and fractional divisors are calculated through the divisor REF D = × 16 BaudRate where f is the reference frequency input to the baud- REF rate ...
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SPI/I In multidrop mode, also known as 9-bit mode, the word length is 8 bits and a 9th bit is used for distinguishing between an address and a data word. Multidrop mode is enabled through MODE2[6]: MultiDrop. Parity checking is ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator RTS/CLKOUT SETUP TX Figure 10. Setup and Hold Times in Auto Transceiver Direction Control Echo Suppression The MAX3107 can suppress echoed data, sometimes found in half-duplex communication (e.g., RS-485 and ...
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SPI RTS/CLKOUT Figure 12. Echo Suppression Timing RESUME are programmed in FlowLvl. With differing HALT and RESUME levels, hysteresis can be defined for the RTS/CLKOUT transitions. When the RxFIFO fill level reaches the HALT level (FlowLvl[3:0]), the MAX3107 ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator If auto transmitter control (FlowCtrl[5:4]) is enabled, the receiver compares all received words with the XOFF and XON characters XOFF is received, the MAX3107 halts its transmitter from ...
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SPI/I Interrupt Structure The structure of the interrupt is shown in Figure 13. There are four interrupt source registers: ISR, LSR, STSInt, and SpclCharInt. The interrupt sources are divided into top- level and low-level interrupts. The top-level interrupts typically occur ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator THR—Transmit Hold Register ADDRESS: 0x00 MODE: W BIT 7 6 TData7 TData6 NAME RESET 0 0 Bits 7–0: TData[7:0] The THR is the register that the host controller writes data ...
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SPI/I Bit 0: LSRErrlEn The LSRErrIEn bit enables IRQ interrupt generation when the LSRErrInt interrupt bit is set in the ISR[0]. Set LSRErrIEn low to disable IRQ generation from LSRErrInt. ISR—Interrupt Status Register ADDRESS: 0x02 MODE: COR BIT 7 6 ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator LSRIntEn—Line Status Register Interrupt Enable ADDRESS: 0x03 MODE: R/W BIT 7 6 NAME — — RESET 0 0 The LSRIntEn allows routing of LSR interrupt bits to the ISR[0]. Bits ...
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SPI/I LSR—Line Status Register ADDRESS: 0x04 MODE BIT NAME — CTSbit RESET X 0 The LSR shows all errors related to the oldest word in the RxFIFO, waiting to be read out of the RHR. The LSR ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator Bit 0: RTimeout The RTimeout bit indicates that stale data is present in the receive FIFO. RTimeout is set when the youngest character resides in the RxFIFO for longer than ...
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SPI/I SpclCharInt—Special Character Interrupt Register ADDRESS: 0x06 MODE: COR 7 6 BIT NAME — — RESET 0 0 Bits 7 and 6: No Function Bit 5: MultiDropInt The MultiDropInt interrupt is set when the MAX3107 receives an address character in ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator STSIntEn—STS Interrupt Enable Register ADDRESS: 0x07 MODE: R BIT NAME — SleepIntEn RESET 0 0 Bits 7 and 4: No Function Bit 6: SleepIntEn Set the SleepIntEn bit ...
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SPI/I MODE1 Register ADDRESS: 0x09 MODE: R/W BIT 7 6 NAME IRQSel AutoSleep RESET 0 0 Bit 7: IRQSel Depending on the logic level of the IRQSel bit, IRQ has different meanings. After a hardware or software (MODE2[0]) reset, the ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator MODE2 Register ADDRESS: 0x0A MODE: R/W BIT 7 6 NAME EchoSuprs MultiDrop RESET 0 0 Bit 7: EchoSuprs Set the EchoSuprs bit high so that the MAX3107’s receiver gates any ...
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SPI/I LCR—Line Control Register ADDRESS: 0x0B MODE: R/W BIT 7 6 NAME TxBreak RTS RESET 0 0 Bit 7: RTS The RTS bit gives direct control of the RTS/CLKOUT output logic. If the RTS bit is set high, then RTS/CLKOUT ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator RxTimeOut—Receiver Timeout Register ADDRESS: 0x0C MODE: R/W BIT 7 6 NAME TimOut7 TimOut6 RESET 0 0 Bits 7–0: TimOut[7:0] The receive data timeout bits allow programming a time delay after ...
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SPI/I IrDA Register ADDRESS: 0x0E MODE: R/W BIT 7 6 NAME — — RESET 0 0 The IrDA allows selection of IrDA SIR and MIR-compliant pulse shaping at the TX and RX interfaces. It also allows inversion of the TX ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator FIFOTrgLvl—FIFO Interrupt Trigger Level Register ADDRESS: 0x10 MODE: R/W BIT 7 6 NAME RxTrig3 RxTrig2 RESET 1 1 Bits 7–4: RxTrig[3:0] These 4 bits allow definition of the receive FIFO ...
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SPI/I FlowCtrl—Flow Control Register ADDRESS: 0x13 MODE: R/W BIT 7 6 NAME SwFlow3 SwFlow2 RESET 0 0 Bits 7–4: SwFlow[3:0] The SwFlow[3:0] bits configure auto software flow control and/or special character detection in combination with the characters defined in the ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator Table 3. SwFlow[3:0] Truth Table SwFlow3 SwFlow2 SwFlow1 RECEIVER FLOW CONTROL CHARACTER DETECTION ...
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SPI/I XON2 Register ADDRESS: 0x15 MODE: R/W BIT 7 6 NAME Bit7 Bit6 RESET 0 0 The XON1 and XON2 register contents define the XON characters for auto XON/XOFF flow control and/or the special characters used in special character detection. ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator XOFF2 Register ADDRESS: 0x17 MODE: R/W BIT 7 6 NAME Bit7 Bit6 RESET 0 0 The XOFF1 and XOFF2 register contents define the XOFF characters for auto XON/XOFF flow control ...
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SPI/I PLLConfig—PLL Configuration Register ADDRESS: 0x1A MODE: R/W BIT 7 6 NAME PLLFactor1 PLLFactor0 RESET 0 0 Bits 7 and 6: PLLFactor[1:0] The two PLLFactor[1:0] bits allow programming with select PLL’s multiplication factor. The input and output frequencies of the ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator BRGConfig—Baud-Rate Generator Configuration Register ADDRESS: 0x1B MODE: R/W BIT 7 6 NAME — — RESET 0 0 Bits 7 and 6: No Function Bit 5: 4xMode When the 4xMode bit ...
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SPI/I CLKSource—Clock Source Register ADDRESS: 0x1E MODE: R/W BIT 7 6 NAME CLKtoRTS — RESET 0 0 Bit 7: CLKtoRTS Set the CLKtoRTS bit route the baud-rate generator (16x baud rate) output clock to RTS/CLKOUT. The clock ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator Serial Controller Interface The MAX3107 can be controlled through SPI or I defined by the logic on I2C/SPI. See the Pin Configurations for further details. The SPI supports both single-cycle ...
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SPI/I S SCL SDA 2 Figure 17 START, STOP, and Repeated START Conditions 2 Table Address Map READ/ DIN/A1 CS/A0 WRITE ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator WRITE SINGLE BYTE S FROM MASTER TO STAVE Figure 18. Write Byte Sequence BURST WRITE S DEVICE SLAVE ADDRESS - W FROM MASTER TO STAVE Figure 19. Burst Write Sequence ...
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SPI/I BURST READ S Sr FROM MASTER TO STAVE Figure 21. Burst Read Sequence S SCL 1 2 NOT ACKNOWLEDGE SDA ACKNOWLEDGE Figure 22. Acknowledge 7) The master sends the 7-bit slave ID plus a read bit (high). 8) The ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator POWER-UP/ RST INPUT PULLED HIGH/ RST BIT SET LOW IS IRQ HIGH? OR RevID READ SUCCESSFULLY Y CONFIGURE CLOCKING CONFIGURE MODES Figure 23. Startup and Initialization Flowchart Low-Power Operation To ...
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SPI MICROCONTROLLER Figure 24. Logic-Level Translation TX MAX3107 MAX13481E D- Figure 25. Connector Sharing with a USB Transceiver Connector Pin Sharing The TX and RTS/CLKOUT outputs can be programmed to be high impedance. This can ...
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SPI/I C UART with 128-Word FIFOs and Internal Oscillator MICROCONTROLLER Figure 26. RS-232 Application 10kΩ MICROCONTROLLER Figure 27. RS-485 Half-Duplex Application 50 _____________________________________________________________________________________ TX 2 SPI MAX3107 RST RTS/CLKOUT CTS IRQ GPIO0 GPIO1 LDOEN GPIO2 GPIO3 3.3V ...
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SPI LDOEN LDO I2C/SPI DIN/A1 DOUT/SDA CS/A0 SCLK/SCL LOGIC-LEVEL TRANSLATION RST IRQ XIN CRYSTAL OSCILLATOR XOUT INTERNAL OSCILLATOR AGND For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 52 2010 Maxim Integrated Products © ...