MAX3107ETG+ Maxim Integrated Products, MAX3107ETG+ Datasheet - Page 40
![IC UART SPI/I2C 128 FIFO 24TQFN](/photos/17/83/178344/qfn24_sml.jpg)
MAX3107ETG+
Manufacturer Part Number
MAX3107ETG+
Description
IC UART SPI/I2C 128 FIFO 24TQFN
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX3107EAG.pdf
(52 pages)
Specifications of MAX3107ETG+
Features
Internal Oscillators
Number Of Channels
4, QUART
Fifo's
128 Byte
Protocol
RS232, RS485
Voltage - Supply
2.35 V ~ 3.6 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
Mounting Type
Surface Mount
Package / Case
24-TQFN Exposed Pad
Data Rate
24 Mbps
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.35 V
Supply Current
0.64 mA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
1
Uart Features
128-Word Transmit / Receive FIFO, Half-Duplex Echo Suppression, Shutdown And Autosleep Modes
Supply Voltage Range
2.35V To 3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SPI/I
and Internal Oscillator
XOFF2 Register
The XOFF1 and XOFF2 register contents define the XOFF characters for auto XON/XOFF flow control and/or special
characters used in special character detection. See details in the FlowCtrl register description.
Bits 7–0: Bit[7:0]
These bits define the XOFF2 character if auto software flow control is enabled in FlowCntrl[7:4]. If double-char-
acter flow control is selected in FlowCntrl[7:4], these bits constitute the MSB of the XOFF character. If special
character detection is enabled in MODE2[4] and auto flow control is not enabled, these bits define a special
character. If both special character detection and auto flow control are enabled (MODE2[4] and FlowCntrl[3]),
these bits define a special character.
GPIOConfg—GPIO Configuration Register
The four GPIOs can be configured as inputs or outputs and can be operated in push-pull or open-drain mode. The
reference clock has to be active for the GPIOs to work.
Bits 7–4: GP[3:0]OD
Set the GP[3:0]OD bits to 1 to configure open-drain output or input operation. If GP[3:0]OD are 0 (default), the
GPIO_are push-pull outputs, if configured as outputs in GPIOConfg[3:0]. If configured as inputs in GPIOConfg[3:0],
the GPIO_ are high-impedance inputs with weak pulldowns.
Bits 3–0: GP[3:0]Out
The GP[3:0]Out bits configure the GPIO_ to be inputs or outputs. Set the GP[3:0]Out bits high to configure the associ-
ated GPIO_ as outputs. The GP[3:0]Out bits which are set low, are configured to be inputs.
GPIOData—GPIO Data Register
Bits 7–4: GPI[3:0]Dat
The GPI[3:0]Dat bits reflect the logic on GPIO_ when configured as inputs through GPIOConfg[3:0].
Bits 3–0: GPO[3:0]Dat
The GPO[3:0]Dat bits allows programming the logic state of the GPIO_, when these are configured as outputs through
GPIOConfg[3:0]. For open-drain operation, pullup resistors are needed on GPIO_.
40
ADDRESS:
MODE:
ADDRESS:
MODE:
ADDRESS:
MODE:
RESET
RESET
RESET
NAME
NAME
NAME
_____________________________________________________________________________________
BIT
BIT
BIT
2
C UART with 128-Word FIFOs
GPI3Dat
GP3OD
Bit7
7
0
7
0
7
0
0x17
R/W
0x18
R/W
0x19
R/W
GPI2Dat
GP2OD
Bit6
6
0
6
0
6
0
GPI1Dat
GP1OD
Bit5
5
0
5
0
5
0
GPI0Dat
GP0OD
Bit4
4
0
4
0
4
0
GPO3Dat
GP3Out
Bit3
3
0
3
0
3
0
GPO2Dat
GP2Out
Bit2
2
0
2
0
2
0
GPO1Dat
GP1Out
Bit1
1
0
1
0
1
0
GPO0Dat
GP0Out
Bit0
0
0
0
0
0
0